LP6280

Page 3 of 12

LP6280–00

Version 0.1 DEC.-2016 Email: marketing@lowpowersemi.com www.lowpowersemi.com

Preliminary Datasheet

Function Block Diagram

ENP

CFY1

VOUT

ENN

AGND

SW

VOP

Sync

Boost

LDO

VIN

PGND

CFY2

VON

SDA

SCL

Control

Logic

Neg-CP

Figure 3. Internal Function Block Diagram

Functional Pin Description

Pin No.

Pin Name

Description

A1

ENN

Logic control shutdown input for VON power control.

A2

VON

Negative voltage output.

A3

CFY2

Negative input for the external flying capacitor. Connect a ceramic 2.2μF capacitor

close to the pins of the IC

B1

ENP

Logic controlled shutdown input for VOP power control.

B2

SCL

IIC interface clock signal. (This pin is for production test only, no connection)

B3,E1

PGND

Boost converter power ground.

C1

VIN

Input supply p

in. Decouple with 4.7μF ceramic capacitor close to the pin.

C2

SDA

IIC interface data signal. (This pin is for production test only, no connection)

C3

CFY1

Positive input for the external flying capacitor. Connect a ceramic 2.2μF capacitor

close to the pins of the IC

D1

SW

Power switching output. Connect an external inductor to this switching node.

D2

AGND

Analog ground. Control circuitry returns current to this pin.

D3,E2

VOUT

Output of the synchronous r

ectifier. Decouple with an external capacitor. At least 4.7μF

is recommended.

Higher capacitor values reduce output ripple.

E3

VOP

Positive voltage output.