LP6280

Page 7 of 12

LP6280–00

Version 0.1 DEC.-2016 Email: marketing@lowpowersemi.com www.lowpowersemi.com

Preliminary Datasheet

Application Information

The LP6280 is a dual channel power sources for LCD

panel. It contains a boost, a LDO and a negative

charge pump. The output voltage of boost converter is

VOUT. The LDO generates the positive voltage(VOP)

and the negative charge pump generates the

negative voltage(VON), both are regulating through

VOUT.

Under Voltage Lockout (UVLO)

The LP6280 had an UVLO internal circuit that enable

the device once the voltage on the VIN voltage

exceeds the UVLO threshold voltage.

Power Sequencing

The LDO (VOP) and the negative charge pump

(VON) are turn on/off by external signal. ENP is for

VOP and ENN is for VON. Beside, any enable signal

turn on, the boost will be power on.

Boost Converter

The LP6280 integrates a PWM synchronous boost

converter

operating

with

current

mode

control.

Switching frequency is 1.2MHz (typ.). The device is

designed for high efficiency over wide output current

range.

VOP/N Discharge

When VIN falls below UVLO threshold or ENP/ENN

becomes low, all converter will be turns off. Both ENP

and

ENN

go

low,

VOP/VON

will

be

actively

discharged to GND with normal set.

Over Temperature Protection

The

LP6280

device

enters

over

temperature

protection if its junction temperature exceeds 140°C

(typical). During over temperature protection none of

the device's functions are available. To resume

normal operation the

junction temperature need

cool down, and the outputs will restart.

Layout Consideration

The proper PCB layout and component placement

are critical for all circuit. The careful attention

should be prevent electromagnetic interference

(EMI) problems. Here are some suggestions to the

layout of LP6280 design.

1. Connected all ground together with one

uninterrupted ground plane, which include power

ground and analog ground.

2. The input capacitor should be located as closed

as possible to the VIN and ground plane.

3. Minimize the distance of all traces connected to

the LX node, that the traces short and wide route

to obtain optimum efficiency.

4. The CFLY should be placed close to IC's

CFLY1 and CFLY2 pins.

5. All output capacitor must be closed to ground

as closed as possible to ground plane.

D1

B1

B3

C1

C3

A1

A2

A3

D3

E1

E2

E3

B2

C2

D2

L

PGND

VIN

LP6280

Figure 9. Recommended PCB Layout Diagram