LP6280

Page 8 of 12

LP6280–00

Version 0.1 DEC.-2016 Email: marketing@lowpowersemi.com www.lowpowersemi.com

Preliminary Datasheet

Application Information (Continued)

1. IIC Interface Specification

The LP6280 can easily modify parameters by IIC bus, that slave address is 0x3EH.

IIC is a two wire serial interface developed, the bus consists of a clock line(SCL) and a data line(SDA) with

pull-up structures. The LP6280 works as a slave mode, and address is 3E. The data transfer protocol is

follow IIC-Bus Specification's standard mode(100kbps) and fast mode(400kbps).

DATA

CLK

S

START condition

P

STOP condition

Figure 10. START and STOP Conditions

DATA

CLK

Data line

stable;

data valid

Change

of data

allowed

Figure 11. Bit Transfer on the Serial Interface

2. Write Data to Register

SCL

SDA

A6

A5

A4

A3

A2

A1

A0

R/W ACK

A6

A5

A4

A3

A2

A1

A0

A7

ACK

0

Slave Address

(0x3E + W )

Register Address

Start

1

1

0

1

1

1

1

1

0

1

7

8

D6

D5

D4

D3

D2

D1

D0

D7

ACK

Data

Stop

1

8

Figure 12. Write Data to Register

3. Read Data to Register

SCL

SDA

A6

A5

A4

A3

A2

A1

A0

R/W ACK

A6

A5

A4

A3

A2

A1

A0

A7

ACK

0

Slave Address

(0x3E + W )

Register Address

Start

1

1

0

1

1

1

1

1

0

1

7

8

ACK

1

8

D6

D5

D4

D3

D2

D1

D0

D7

ACK

Data

Stop

1

8

1

Slave Address

(0x3E + R )

0

1

1

1

1

1

0

A6

A5

A4

A3

A2

A1

A0

R/W

Sr

Figure 13. Read Data from Register