CYUSB306X datasheet(18/37 Pages) CYPRESS

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CYUSB306X

Document Number: 001-87516 Rev. *L

Page 18 of 37

IIX

Input leakage current for all pins

except

SSTXP/SSXM/SSRXP/SSRXM

–1

µA

All I/O signals held at VDDQ

(For I/Os with a pull-up or pull-down

resistor connected, the leakage

current increases by VDDQ/RPU or

VDDQ/RPD)

IOZ

Output High-Z leakage current for

all pins except SSTXP/ SSXM/

SSRXP/SSRXM and MIPI CSI-2

signals

–1

µA

All I/O signals held at VDDQ

ICC Core

Core and analog voltage

operating current

–

192

mA Total current through AVDD, VDD

ICC USB

USB voltage supply operating

current

–60

–

ISB1

Total suspend current during

suspend mode with USB 3.0 PHY

enabled

Core: 558.35 µA

–

µA

Core Current is measured through

VDD, AVDD and VDD_MIPI.

I/O Current is measured through

VDDIO1 to VDDIO3.

USB Current is measured through

VUSB, U3TXVDDQ and U3RXVDDQ.

I/O: 4.58 µA

–

µA

USB: 4672 µA

–

µA

ISB3

Total standby current during core

power-down mode

Core: 148.31 µA

–

µA

I/O: 3.16 µA

–

µA

USB: 15.8 µA

–

µA

VRAMP

Voltage ramp rate on core and I/O

supplies

0.2

V/ms Voltage ramp must be monotonic

Noise level permitted on VDD and

I/O supplies

–

100

mV Max p-p noise level permitted on all

supplies except AVDD

VN_AVDD

Noise level permitted on AVDD

supply

–20

mV Max p-p noise level permitted on

AVDD

DC Specifications (continued)

Parameter

Description

Min

Max

Units

Notes

MIPI D-PHY Electrical Characteristics

Parameter

Description

Spec

Unit

Min

Nom

Max

MIPI D-PHY RX DC Characteristics

VPIN

Pin signal voltage range

–50

–

1350

VIH

Logic 1 input voltage

880

–

VIL

Logic 0 input voltage

–

550

VCMRX (DC)

Common-mode voltage HS receiver mode

–

330

VIDTH

Differential input high threshold

–

VIDTL

Differential input low threshold

–70

–

VIHHS

Single-ended input high voltage

–

460

VILHS

Single-ended input low voltage

–40

–

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