CYUSB306X datasheet(13/37 Pages) CYPRESS

13 / 37 page

CYUSB306X

Document Number: 001-87516 Rev. *L

Page 13 of 37

Configuration Options

Configuration options are available for specific usage models.

Contact Cypress Marketing (usb3@cypress.com) for details.

Digital I/Os

CX3 has internal firmware-controlled pull-up or pull-down

resistors on all digital I/O pins. An internal 50-k

 resistor pulls

the pins high, while an internal 10-k

 resistor pulls the pins low

to prevent them from floating. The I/O pins may have the

following states:

■ Tristated (High-Z)

■ Weak pull-up (via internal 50 k)

■ Pull-down (via internal 10 k)

■ Hold (I/O hold its value) when in low-power modes

■ The JTAG TDI, TMC, and TRST# signals have fixed 50-k

internal pull-ups, and the TCK signal has a fixed 10-k



pull-down resistor.

All unused I/Os should be pulled high by using the internal

pull-up resistors. All unused outputs should be left floating. All

I/Os can be driven at full-strength, three-quarter strength,

half-strength, or quarter-strength. These drive strengths are

configured separately for each interface.

GPIOs

CX3 provides 12 pins for general purpose I/O (for example, can

be used for lighting, sync-in, sync-out and so on). See Pin

Configuration on page 14 for pinout details.

All GPIO pins support an external load of up to 16 pF for every

pin.

EMI

CX3 can meet EMI requirements outlined by FCC 15B (USA)

and EN55022 (Europe) for consumer electronics at system level.

CX3 can tolerate reasonable EMI, conducted by the aggressor,

outlined by these specifications and continue to function as

expected.

System-level ESD

CX3 has built-in ESD protection on the D+, D–, and GND pins

on the USB interface. The ESD protection levels provided on

these ports are:

■ ±2.2-kV human body model (HBM) based on JESD22-A114

specification

■ ±6-kV contact discharge and ±8-kV air gap discharge based

on IEC61000-4-2 level 3A using external system-level

protection devices

■ ± 8-kV contact discharge and ±15-kV air gap discharge based

on IEC61000-4-2 level 4C using external system-level

protection devices

This protection ensures that the device continues to function

after ESD events up to the levels stated in this section.

The SSRX+, SSRX–, SSTX+, and SSTX– pins only have up to

±2.2-kV HBM internal ESD protection.

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