CYUSB306X datasheet(7/37 Pages) CYPRESS

7 / 37 page

CYUSB306X

Document Number: 001-87516 Rev. *L

Page 7 of 37

MIPI CSI-2 RX Interface

The Mobile Industry Processor Interface (MIPI) association

defined the Camera Serial Interface 2 (CSI-2) standard to enable

image data to be sent on high-bandwidth serial lines.

CX3 implements a MIPI CSI-2 Receiver with the following

features:

1. It can receive clock and data in 1, 2, 3, or 4 lanes.

(CYUSB3065 part supports up to four lanes; CYUSB3064 part

supports up to two lanes)

2. Up to 1 Gbps of data on each CSI lane is supported (total

maximum bandwidth should not exceed 2.4 Gbps).

3. Video formats such as RAW8/10/12/14, YUV422 (CCIR/ITU

8/10-bit), RGB888/666/565, and User-Defined 8-bit are

supported

4. A CCI interface (compatible with 100-kHz or 400-kHz I2C

interface with 7-bit addressing) is provided to configure the

sensor.

5. GPIOs are available for synchronization of external flash or

lighting system with image sensors to illuminate the scene

that improves the image quality by improving Signal to noise

ratio.

6. GPIOs can also be used to synchronize the image sensor with

external events, so that image can be captured based on

external event.

7. Serial interfaces (such as I2C, I2S, SPI, UART) are available

to implement camera functions such as Auto focus and Pan,

Tilt, Zoom (PTZ)

Additional Outputs

In addition to the standard MIPI CSI-2 signals, the following three

additional outputs are provided:

1. XRST: this can be used to reset the image sensor

2. XSHUTDOWN: this pin can be used to put the sensor to a

standby/shutdown mode

3. MCLK: this pin can provide the clock output. It can be used

only for testing the image sensor. For production, use an

external clock generator as clock input for image sensors.

CPU

CX3 has an on-chip 32-bit, 200-MHz ARM926EJ-S core CPU.

The core has direct access to 16 kB of Instruction Tightly

Coupled Memory (TCM) and 8 kB of data TCM. The

ARM926EJ-S core provides a JTAG interface for firmware

debugging.

CX3 offers the following advantages:

■ Integrates 512 KB of embedded SRAM for code and data and

8 kB of instruction cache and data cache.

■ Implements efficient and flexible DMA connectivity between the

various peripherals (such as, USB, CSI-2 Rx, I2S, SPI, and

UART), requiring firmware only to configure data accesses

between peripherals, which are then managed by the DMA

fabric.

■ Allows easy application development on industry-standard

development tools for ARM926EJ-S.

Examples of the CX3 firmware are available with the Cypress

EZ-USB CX3 Development Kit. Software APIs that can be ported

to an external processor are available with the Cypress EZ-USB

CX3 Software Development Kit.

JTAG Interface

CX3’s JTAG interface has a standard five-pin interface to

connect to a JTAG debugger in order to debug firmware through

the CPU-core's on-chip-debug circuitry.

Industry-standard debugging tools for the ARM926EJ-S core

can be used for the CX3 application development.

Other Interfaces

CX3 supports the following serial peripherals:

■ UART

■ I2C

■ I2S

■ SPI

The CYUSB306X Pin List on page 15 shows the details of how

these interfaces are mapped.

UART Interface

The UART interface of CX3 supports full-duplex communication.

It includes the signals noted in Table 1.

The UART is capable of generating a range of baud rates, from

300 bps to 4608 Kbps, selectable by the firmware. If flow control

is enabled, then CX3's UART only transmits data when the CTS

input is asserted. In addition to this, CX3's UART asserts the RTS

output signal, when it is ready to receive data.

I2C Interface

CX3’s I2C interface is compatible with the I2C Bus Specification

Revision 3. This I2C interface is capable of operating only as I2C

master; therefore, it may be used to communicate with other I2C

slave devices. For example, CX3 may boot from an EEPROM

connected to the I2C interface, as a selectable boot option.

CX3’s I2C Master Controller also supports multi-master mode

functionality.

The power supply for the I2C interface is VDDIO1, which is a

separate power domain from the other serial peripherals. This

gives the I2C interface the flexibility to operate at a different

voltage than the other serial interfaces.

Table 1. UART Interface Signals

Signal

Description

Output signal

Input signal

CTS

Flow control

RTS

Flow control

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