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CYUSB302X датащи(PDF) 26 Page - Cypress Semiconductor |
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CYUSB302X датащи(HTML) 26 Page - Cypress Semiconductor |
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26 / 34 page ![]() Document Number: 001-55190 Rev. *L Page 26 of 34 CYUSB302x Reset Sequence Table 14 provides the hard reset sequence requirements for SD3. Figure 7. Reset Sequence Table 14. Reset and Standby Timing Parameters Parameter Definition Conditions Min (ms) Max (ms) tRPW Minimum RESET# pulse width Clock Input 1 – Crystal Input 1 – tRH Minimum high on RESET# – 5 – tRR Reset Recovery Time (after which Boot loader begins firmware download) Clock Input 1 – Crystal Input 5 tSBY Time to enter Standby/Suspend (from the time MAIN_CLOCK_EN/ MAIN_POWER_EN bit is set) – – 1 tWU Time to wakeup from standby Clock Input 1 – Crystal Input 5 – tWH Minimum time before Standby/Suspend source may be reasserted – 5 – VDD (core ) xVDDQ XTALIN/ CLKIN RESET # Mandatory Reset Pulse Hard Reset tRPW tRh Standby/ Suspend Source Standby/Suspend source Is asserted (MAIN_POWER_EN/ MAIN_CLK_EN bit is set) Standby/Suspend source Is deasserted tSBY tWU XTALIN/ CLKIN must be stable before exiting Standby/Suspend tRR tWH |
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