CYUSB302X datasheet(19/34 Pages) CYPRESS

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Document Number: 001-55190 Rev. *L

Page 19 of 34

CYUSB302x

I2C Fast Mode Parameters

fSCL

SCL clock frequency

400

kHz

tHD:STA

Hold time START condition

0.6

–

µs

tLOW

LOW period of the SCL

1.3

–

µs

tHIGH

HIGH period of the SCL

0.6

–

µs

tSU:STA

Setup time for a repeated START condition

0.6

–

µs

tHD:DAT

Data hold time

–

µs

tSU:DAT

Data setup time

100

–

Rise time of both SDA and SCL signals

–

300

Fall time of both SDA and SCL signals

–

300

tSU:STO

Setup time for STOP condition

0.6

–

µs

tBUF

Bus-free time between a STOP and START condition

1.3

–

µs

tVD:DAT

Data valid time

–

0.9

µs

tVD:ACK

Data valid ACK

–

0.9

µs

tSP

Pulse width of spikes that must be suppressed by input filter

I2C Fast Mode Plus Parameters (Not supported at I2C_VDDQ = 1.2V)

fSCL

SCL clock frequency

1000

kHz

tHD:STA

Hold time START condition

0.26

–

µs

tLOW

LOW period of the SCL

0.5

–

µs

tHIGH

HIGH period of the SCL

0.26

–

µs

tSU:STA

Setup time for a repeated START condition

0.26

–

µs

tHD:DAT

Data hold time

–

µs

tSU:DAT

Data setup time

–

µs

Rise time of both SDA and SCL signals

–

120

Fall time of both SDA and SCL signals

–

120

tSU:STO

Setup time for STOP condition

0.26

–

µs

tBUF

Bus free time between a STOP and START condition

0.5

–

µs

tVD:DAT

Data valid time

–

0.45

µs

tVD:ACK

Data valid ACK

–

0.55

µs

tSP

Pulse width of spikes that must be suppressed by input filter

Table 10. I2C Timing Parameters[4] (continued)

Parameter

Description

Min

Max

Units

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