4100 datasheet(15/43 Pages) CYPRESS

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Document Number: 001-87220 Rev. *J

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PSoC® 4: PSoC 4100 Family

Datasheet

Power

The following power system diagrams show the minimum set of

power supply pins as implemented for PSoC 4100. The system

has one regulator in Active mode for the digital circuitry. There is

no analog regulator; the analog circuits run directly from the

VDDA input. There are separate regulators for the Deep Sleep

and Hibernate (lowered power supply and retention) modes.

There is a separate low-noise regulator for the bandgap. The

supply voltage range is 1.71 V to 5.5 V with all functions and

circuits operating over that range.

Figure 10. PSoC 4 Power Supply

The PSoC 4100 family allows two distinct modes of power supply

operation: Unregulated External Supply, and Regulated External

Supply modes.

Unregulated External Supply

In this mode, PSoC 4100 is powered by an external power supply

that can be anywhere in the range of 1.8 V to 5.5 V. This range

is also designed for battery-powered operation, for instance, the

chip can be powered from a battery system that starts at 3.5 V

and works down to 1.8 V. In this mode, the internal regulator of

PSoC 4100 supplies the internal logic and the VCCD output of the

PSoC 4100 must be bypassed to ground via an external

Capacitor (in the range of 1 µF to 1.6 µF; X5R ceramic or better).

VDDA and VDDD must be shorted together; the grounds, VSSA

and VSS must also be shorted together. Bypass capacitors must

be used from VDDD to ground, typical practice for systems in this

frequency range is to use a capacitor in the 1-µF range in parallel

with a smaller capacitor (0.1 µF for example). Note that these are

simply rules of thumb and that, for critical applications, the PCB

layout, lead inductance, and the Bypass capacitor parasitic

should be simulated to design and obtain optimal bypassing.

Figure 11. 48-TQFP Package Example

Figure 12. 44-TQFP Package Example

Analog

Domain

VDDA

VSSA

VDDA

1.8 Volt

Reg

VDDD

VSSD

VDDD

VCCD

Digital

Domain

Power Supply

Bypass Capacitors

VDDD–VSS

0.1 µF ceramic at each pin (C2, C6) plus

bulk capacitor 1 to 10 µF (C1). Total capac-

itance may be greater than 10 µF.

VDDA–VSSA

0.1 µF ceramic at pin (C4). Additional

1 µF to 10 µF (C3) bulk capacitor. Total

capacitance may be greater than 10 µF.

VCCD–VSS

1 µF ceramic capacitor at the VCCD pin

(C5)

VREF–VSSA

(optional)

The internal bandgap may be bypassed

with a 1 µF to 10 µF capacitor. Total capac-

itance may be greater than 10 µF.

C2 0.1 µF

GROUND

1 µF C1

C5 1 µF

0.1 µF C4

C3 1 µF

GROUND

C3 1 µF

0.1 µF C4

(GPIO)P1.7/VREF1 ?

XRES

(GPIO) P2.0

235

(GPIO) P0.7

(GPIO) P2.1

334

(GPIO) P0.6

(GPIO) P2.2

433

(GPIO) P0.5

(GPIO) P2.3

48 TQFP

(GPIO) P0.4

(GPIO) P2.4

631

(GPIO) P0.3

(GPIO) P2.5

730

(GPIO) P0.2

(GPIO) P2.6

829

(GPIO) P0.1

(GPIO) P2.7

928

(GPIO) P0.0

(GPIO) P3.0

(GPIO) P4.3

Top View

TQ FP

(Top View )

VSS

(GPIO)P2[0]

(GPIO)P2[1]

(GPIO)P2[2]

(GPIO)P2[3]

(GPIO)P2[4]

(GPIO)P2[5]

(GPIO)P2[6]

(GPIO)P2[7]

(GPIO)P3[0]

(GPIO) P4[3]

(GPIO) P0[0]

(GPIO) P0[1]

(GPIO) P0[2]

(GPIO) P0[3]

(GPIO) P0[4]

(GPIO) P0[5]

(GPIO) P0[7]

XRES

(GPIO) P0[6]

C2 0.1 µF

VSS

1 µF C1

VSS

C5 1 µF

VSS

VC CD

C6 0.1 µF

VSS

0.1 µF C4

C3 1 µF

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