AM29PDL128G80 datasheet(45/69 Pages) SPANSION

45 / 69 page

Am29PDL128G

July 29, 2002

P R E L I M I NARY

Legend:

DYB = Dynamic Protection Bit

SSA = SecSi Sector Address (A6:A0) is (0011010).

PD[3:0] = Program Data. Password written as four 16-bit sections.

PPB = Persistent Protection Bit

PWA = Password Address. A0:A-1 selects portion of password.

PWD = Password Data being verified.

PL = Password Protection Mode Lock Address (A5:A0) is (001010)

RD(0) = Read Data DQ0 for protection indicator bit.

RD(1) = Read Data DQ1 for PPB Lock bit status.

SA = Sector Address where security command applies. Address bits

A21:A11 uniquely select any sector.

SL = Persistent Protection Mode Lock Address (A5:A0) is (010010)

WP = PPB Address (A6:A0) is (0111010) (Note 16)

EP = PPB Erase Address (A6:A0) is (1111010)

X = Don’t care

PPMLB = Password Protection Mode Locking Bit

SPMLB = Persistent Protection Mode Locking Bit

See Table 1 for description of bus operations.

All values are in hexadecimal.

Shaded cells in table denote read cycles. All other cycles are

write operations.

During unlock and command cycles, when lower address bits are

555 or AAAh as shown in table, address bits higher than A11

(except where BA is required) and data bits higher than DQ7 are

don’t cares.

Reset command returns device to reading array.

Cycle 4 programs addressed locking bit. Cycles 5 and 6 validate

the bit has been fully programmed when DQ0 = 1. If DQ0 = 0 in

cycle 6, the program command must be issued and verified again.

Data is latched on rising edge of WE#.

Entire command sequence must be executed for each portion of

password.

Command sequence returns FFh if PPMLB is set.

10. Password is written over four consecutive cycles, at addresses

0-3.

11. A 2 µs timeout is required between any two portions of password.

12. A 100 µs timeout is required between cycles 4 and 5.

13. A 1.2 ms timeout is required between cycles 4 and 5.

14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been

fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, erase command

must be issued and verified again. Before issuing erase

command, all PPBs should be programmed in order to prevent

PPB overerasure.

15. DQ1 = 1 if PPB locked, 0 if unlocked.

16. For all other parts that use the Persistant Protection Bit (excluding

PDL640G), the WP address is 000010.

Table 17.

Sector Protection Command Definitions (x16 Mode)

Command (Notes)

Bus Cycles (Notes 1-4)

Addr Data Addr Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Reset

XXX

SecSi Sector Entry

AAA

555

(BA)AAA

SecSi Sector Exit

AAA

555

(BA)AAA

SecSi Protection Bit Program (5, 6)

AAA

555

(BA)AAA

SSA

RD(0)

Password Program (5, 7, 8)

AAA

555

AAA

XX[0-3]

PD[0-3]

Password Verify (8, 9)

AAA

555

AAA

PWA[0-3] PWD[0-3]

Password Unlock (7, 10, 11)

AAA

555

AAA

PWA[0-3] PWD[0-3]

PPB Program (6, 12)

AAA

555

AAA

(SA)WP

(SA)WP RD(0)

All PPB Erase (13, 14)

AAA

555

AAA

(SA)EP

(SA)WP RD(0)

PPB Lock Bit Set

AAA

555

AAA

PPB Lock Bit Status (15)

AAA

555

AAA

RD(1)

DYB Write (7)

AAA

555

AAA

DYB Erase (7)

AAA

555

AAA

DYB or PPB Status

AAA

555

AAA

RD(0)

PPMLB Program (5, 6, 12)

AAA

555

AAA

RD(0)

PPMLB Status (5)

AAA

555

AAA

RD(0)

SPMLB Program (5, 6, 12)

AAA

555

AAA

RD(0)

SPMLB Status (5)

AAA

555

AAA

RD(0)

AM29PDL128G80 датащи(PDF) 45 Page - SPANSION

AM29PDL128G80 датащи(HTML) 45 Page - SPANSION

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69

датащи скачать

ссылки URL