AM29PDL128G80 datasheet(30/69 Pages) SPANSION

30 / 69 page

July 29, 2002

Am29PDL128G

P R E L I M I NARY

The SecSi Sector area can be protected using one of

the following procedures:

s Write the three-cycle Enter SecSi Sector Region

command sequence, and then follow the in-system

sector protect algorithm as shown in Figure 1, ex-

cept that RESET# may be at either V

IH or VID. This

allows in-system protection of the SecSi Sector Re-

gion without raising any device pin to a high voltage.

Note that this method is only applicable to the SecSi

Sector.

s Write the three-cycle Enter SecSi Sector Secure

Region command sequence, and then use the alter-

nate method of sector protection described in the

Sector Protection section.

Once the SecSi Sector is locked and verified, the sys-

tem must write the Exit SecSi Sector Region com-

mand sequence to return to reading and writing the

remainder of the array.

The SecSi Sector lock must be used with caution

since, once locked, there is no procedure available for

unlocking the SecSi Sector area and none of the bits

in the SecSi Sector memory space can be modified in

any way.

SecSi Sector Protection Bit

The SecSi Sector Protection Bit prevents program-

ming of the SecSi Sector memory area. Once set, the

SecSi Sector memory area contents are non-modifi-

able.

Utilizing Password and SecSi Sector Concurrently

The password must be stored in the first eight bytes of

the SecSi Sector. Once the device is permanently

locked into the Password Protection Mode, the erase,

program, and read operation no longer work on those

eight bytes of password in the SecSi Sector. Once the

SecSi Sector protection bit is programmed, no location

in the SecSi Sector may be programmed. To use both

Password Protection and the SecSi Sector concur-

rently, the user must always program the password

into the first eight bytes of the SecSi Sector before ei-

ther the Password Protection Mode is selected or the

SecSi Sector protection bit is programmed.

Method 1

1. Enter the SecSi Sector by issuing the SecSi Sector

Entry command.

2. Program the 64-bit password by issuing the Pass-

word Program and Password Verify commands

3. Lock the password by issuing the Password Protec-

tion Mode Locking Bit Program command.

4. Program the SecSi Sector, excluding bytes 0–7.

5. Lock the SecSi Sector by issuing the SecSi Sector

Protection Bit Program command.

6. Exit the SecSi Sector by issuing the SecSi Sector

Exit or Reset command

Note: Step 4 may be performed prior to step 2.

Method 2

1. Enter the SecSi Sector by issuing the SecSi Sector

Entry command.

2. Program the entire SecSi Sector, including the first

eight bytes contain the 64-bit password.

3. Lock the password by issuing the Password Protec-

tion Mode Locking Bit Program command.

4. Lock the SecSi Sector by issuing the SecSi Sector

Protection Bit Program command.

5. Exit the SecSi Sector by issuing the SecSi Sector

Exit or Reset command

Note: Step 4 may be performed prior to step 3.

Hardware Data Protection

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes. In addition, the following

hardware data protection measures prevent accidental

erasure or programming, which might otherwise be

caused by spurious system level signals during V

power-up and power-down transitions, or from system

noise.

Low VCC Write Inhibit

When V

CC is less than VLKO, the device does not ac-

cept any write cycles. This protects data during V

power-up and power-down. The command register

and all internal program/erase circuits are disabled,

and the device resets to the read mode. Subsequent

writes are ignored until V

CC is greater than VLKO. The

system must provide the proper signals to the control

pins to prevent unintentional writes when V

CC is

greater than V

LKO.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE#

or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

IL, CE# = VIH or WE# = VIH. To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a

logical one.

Power-Up Write Inhibit

If WE# = CE# = V

IL and OE# = VIH during power up,

the device does not accept commands on the rising

edge of WE#. The internal state machine is automati-

cally reset to the read mode on power-up.

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