AD7760

Preliminary Technical Data

Rev. PrN | Page 20 of 22

AD7760 REGISTERS

The AD7760 has a number of user-programmable registers. The control registers are used to set the decimation rate, the filter

configuration, the clock divider etc. There are also digital gain, offset and over-range threshold registers. Writing to these registers

involves writing the register address first, then a 16-bit data word. Register Addresses, details of individual bits and default values are given

here.

Table 12. Control Register 1 (Address 0x0001, Default Value 0x001A)

MSB

LSB

DL

Filt

RD

Ovr

RD

Gain

RD

Off

RD

Stat

CAL

SYNC

FLEN3

FLEN2

FLEN1

FLEN0

BYP F3

BYP F1

DEC2

DEC1

DEC0

Bit

Mnemonic

Comment

15

DL Filt1

Download Filter. Before downloading a user defined filter, this bit must be set. The Filter Length bits must also be set at

this time. The write operations that follow will be interpreted as the user coefficients for the FIR filter until all the

coefficients and the checksum have been written.

14

RD Ovr1,2

Read Overrange. If this bit has been set, the next read operation will output the contents of the Overrange Threshold

Register instead of a conversion result.

13

RD Gain1,2

Read Gain. If this bit has been set, the next read operation will output the contents of the digital Gain Register.

12

RD Off1,2

Read Offset. If this bit has been set, the next read operation will output the contents of the digital Offset Register.

11

RD Stat1,2

Read Status. If this bit has been set, the next read operation will output the contents of the Status Register.

10

CAL1

Calibration. Setting this bit will initiate an internal calibration routine. This routine will take 14mS with a 20MHz ICLK.

9

SYNC1

Synchronize. Setting this bit will initiate in internal synchronisation routine. Setting this bit simultaneously on multiple

devices will synchronize all filters.

8-5

FLEN3:0

Filter Length Bits. These bits must be set when the DL Filt bit is set and before a user defined filter is downloaded.

4

BYP F3

Bypass Filter 3. If this bit is a 0, Filter 3 (Programmable FIR) will be bypassed.

3

BYP F1

Bypass Filter 1. If this bit is a 0, Filter 1 will be bypassed. This should only occur when the user requires unfiltered

modulator data to be output.

2-0

DEC2:0

Decimation Rate. These bits set the decimation rate of Filter 2. All zeros implies that the filter is bypassed. A value of 1

corresponds to 2x decimation, a value of 2 corresponds to 4x and so on up to the maximum value of 5, corresponding

to 32x decimation.

Table 13. Control Register 2 (Address 0x0002, Default Value 0x009B)

MSB

LSB

0

0

0

0

0

0

0

0

0

0

CDIV1

CDIV0

PD

LPWR

1

D1PD

Bit

Mnemonic

Comment

5-4

CDIV1:0

Clock Divider Bits. These set the divide ratio of the MCLK signal to produce the internal ICLK. Setting CDIV[1:0] = 00

divides the MCLK by 2, setting CDIV[1:0] = 01 divides MCLK by 4. If CDIV[1:0] = 10 then the MCLK frequency is equal to

the ICLK. CDIV[1:0] = 11 is not allowed.

3

PD

Power Down. Setting this bit powers down the AD7760 reducing the power consumption to TBD µW.

2

LPWR

Low Power. If this bit is set, the AD7760 is operating in a low power mode. The power consumption is reduced for a 6dB

reduction in noise performance.

1

Write a ‘1’ to this bit.

0

D1PD

Differential Amplifier Power Down. Setting this bit powers down the on-chip differential amplifier.