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AD7760BCP датащи(PDF) 14 Page - Analog Devices |
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AD7760BCP датащи(HTML) 14 Page - Analog Devices |
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14 / 22 page ![]() AD7760 Preliminary Technical Data Rev. PrN | Page 14 of 22 CLOCKING THE AD7760 The AD7760 requires an external low jitter clock source. This signal is applied to the MCLK and MCLK pins. An internal clock signal (ICLK) is derived from the MCLK input signal. This ICLK controls all the internal operation of the AD7760. The maximum ICLK frequency is 20MHz but due to an internal clock divider, a range of MCLK frequencies can be used. There are three possibilities available to generate the ICLK: 1. ICLK = MCLK (CDIV[1:0] = 10) 2. ICLK = MCLK / 2 (CDIV[1:0] = 00) 3. ICLK = MCLK / 4 (CDIV[1:0] = 01) These options are selected from the control register (See Register Section for further details). On power-up, the default is ICLK = MCLK / 4 to ensure that the part can handle the maximum MCLK frequency of 80MHz. If the user wishes to get output data rates equal to those used in audio systems, a 12.288 MHz ICLK frequency can be used. As shown in Table 5, output data rates of 192, 96 and 48kHz are achievable with this ICLK frequency. As mentioned previously, this ICLK frequency can be derived from different MCLK frequencies. The MCLK jitter requirements depend on a number of factors and are given by the following equation: 20 ) ( ) ( 10 2 dB SNR IN RMS j f OSR t × × × = π OSR = Over-sampling ratio = ODR f ICLK fIN = Maximum Input Frequency SNR(dB) = Target SNR. Taking an example from Table 5: ODR = 2.5MHz, fICLK = 20MHz, fIN (max) = 1MHz, SNR = 108dB ps t RMS j 79 . 1 10 10 2 8 4 . 5 6 ) ( = × × × = π This is the maximum allowable clock jitter for a full-scale 1MHz input tone with the given ICLK and Output Data Rate. Taking a second example from Table 5: ODR = 48kHz, fICLK = 12.288MHz, fIN (max) = 19.2kHz, SNR = 120dB ps t RMS j 133 10 10 2 . 19 2 256 6 3 ) ( = × × × × = π The input amplitude also has an effect on these jitter figures. If, for example, the input level was 3dB down from full-scale, the allowable jitter would be increased by a factor of √2 increasing the first example to 2.53ps RMS. This is due to the fact that the maximum slew rate is reduced by a reduction in amplitude. Figure 14 and Figure 15 illustrate this point showing the maximum slew rate of a sine wave of the same frequency but with different amplitudes. Figure 14. Maximum Slew Rate of Sine Wave with Amplitude of 2V Pk-Pk Figure 15. Maximum Slew Rate of Same Frequency Sine Wave with Amplitude of 1V Pk-Pk |
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