Preliminary Technical Data

AD7760

Rev. PrN | Page 9 of 22

TQFP Pin

Number

CSP Pin

Number

Pin Mnemonic

Description

19

13

Positive Input to Full-Power Differential Amplifier 1.

20

14

Negative Input to Full-Power Differential Amplifier 1.

21

15

Negative Output from Full-Power Differential Amplifier 1.

22

16

Positive Output from Full-Power Differential Amplifier 1.

25

18

Positive Input to the Modulator.

26

19

Negative Input to the Modulator.

10

8

Reference Input. The input range of this pin is determined by the reference buffer supply

8

6

DECAP1

Decoupling Pin. A 100nF capacitor must be inserted between this pin and AGND.

29

21

DECAP2

Decoupling Pin. A TBD µF capacitor must be inserted between this pin and AGND.

30

22

DECAP3

Decoupling Pin. A TBD µF capacitor must be inserted between this pin and AGND.

17

12

Bias Current setting pin. A resistor must be inserted between this pin and AGND. For more

details on this, see the Bias Resistor Section.

45-52,

54-61

33-48

DB15 – DB0

16-bit bi-directional data bus. These are three-state pins that are controlled by the CS and RD

Interfacing Section for more details.

37

27

RESET

A falling edge on this pin resets all internal digital circuitry. Holding this pin lows keeps the

AD7760 in a reset state.

3

3

MCLK

Master Clock Input. A low jitter digital clock must be applied to this pin. The output data rate

will depend on the frequency of this clock. See Clocking Section for more details.

2

2

MCLK

Master Clock ground sensing pin.

36

26

SYNC

Synchronization Input. A falling edge on this pin resets the internal filter. This can be used to

synchronize multiple devices in a system.

39

29

RD/WR

Read/Write Input. This pin, in conjunction with the Chip Select pin, is used to read and write

data to and from the AD7760. If this pin is low when CS is low, a read will take place. If this pin

is high and CS is low, a write will occur. See AD7760 Interface Section for more details.

38

28

DRDY

Data Ready Output. Each time that new conversion data is available, an active low pulse,

½ ICLK period wide, is produced on this pin. See AD7760 Interface Section for further details.

40

30

CS

Chip Select Input. Used in conjunction with the RD/WR pin to read and write data to and from

the AD7760. See AD7760 Interface Section for further details.