TMS320VC5507 datasheet(27/135 Pages) TI

27 / 135 page

Introduction

April 2004 − Revised January 2005

SPRS244C

Table 2−3. Signal Descriptions (Continued)

TERMINAL

NAME

RESET

CONDITION

BK‡

FUNCTION

I/O/Z†

MULTIPLEXED

SIGNAL NAME

MULTICHANNEL BUFFERED SERIAL PORTS SIGNALS (CONTINUED)

CLKR2

McBSP2 receive clock. CLKR2 serves as the serial shift clock for the serial

port receiver.

Input

DR2

McBSP2 serial data receive

Input

FSR2

McBSP2 receive frame synchronization. The FSR2 pulse initiates the data

receive process over DR2.

Input

DX2

O/Z

McBSP2 serial data transmit. DX2 is placed in the high-impedance state

when not transmitting, when RESET is asserted, or when OFF is low.

Hi-Z

CLKX2

I/O/Z

McBSP2 transmit clock. CLKX2 serves as the serial shift clock for the

serial port transmitter. The CLKX2 pin is configured as input after reset.

Input

FSX2

I/O/Z

McBSP2 frame synchronization. The FSX2 pulse initiates the data

transmit process over DX2. FSX2 is configured as an input following reset.

Input

USB

I/O/Z

Differential (positive) receive/transmit. At reset, this pin is configured as

input.

Input

I/O/Z

Differential (negative) receive/transmit. At reset, this pin is configured as

input.

Input

O/Z

Pullup output. This pin is used to pull up the detection resistor required by

the USB specification. The pin is internally connected to USBVDD via a

software controllable switch (CONN bit of the USBCTL register).

Hi-Z

A/D

AIN0

Analog Input Channel 0

Input

AIN1

Analog Input Channel 1

Input

AIN2 (BGA only)

Analog Input Channel 2. (BGA package only)

Input

AIN3 (BGA only)

Analog Input Channel 3. (BGA package only)

Input

† I = Input, O = Output, S = Supply, Hi-Z = High-impedance

‡ BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,

PD = pulldown, H = hysteresis input buffer, FS = fail-safe buffer

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