TMS320VC5507 datasheet(33/135 Pages) TI

33 / 135 page

Functional Overview

April 2004 − Revised January 2005

SPRS244C

3.1.4 Memory Maps

3.1.4.1

PGE Package Memory Map

The PGE package features 14 address bits representing 16K-byte linear address for asynchronous memories

per CE space. Due to address row/column multiplexing, address reach for SDRAM devices is 4M bytes for

each CE space. The largest SDRAM device that can be used with the 5507 in a PGE package is 128M-bit

SDRAM.

000000

DARAM / HPI Access

(32K − 192) Bytes

008000

DARAM‡

32K Bytes

010000

SARAM§

64K Bytes

External¶ − CE0

040000

400000

800000

C00000

FF0000

64K Bytes

FFFFFF

External¶ − CE1

External¶ − CE2

External¶ − CE3

Block Size

Byte Address

(Hex)†

(if MPNMC=0)

ROM||

(if MPNMC=1)

External¶ − CE3

16K Bytes − Asynchronous

4M Bytes − SDRAM (MPNMC = 1)

4M Bytes − 64K Bytes if internal ROM selected (MPNMC = 0)

16K Bytes − Asynchronous

4M Bytes − SDRAM

16K Bytes − Asynchronous

4M Bytes − SDRAM

16K Bytes − Asynchronous

4M Bytes − 128K Bytes SDRAM#

Memory Blocks

† Address shown represents the first byte address in each block.

‡ Dual-access RAM (DARAM): two accesses per cycle per block, 8 blocks of 8K bytes.

§ Single-access RAM (SARAM): one access per cycle per block, 8 blocks of 8K bytes.

¶ External memory spaces are selected by the chip-enable signal shown (CE[0:3]). Supported memory types include: asynchronous static

RAM (SRAM) and synchronous DRAM (SDRAM).

# The minus 128K bytes consists of 32K-byte DARAM/HPI access, 32K-byte DARAM, and 64K-byte SARAM.

|| Read-only memory (ROM): one access every two cycles.

0000C0

MMR (Reserved)

020000

Reserved

Figure 3−2. TMS320VC5507 Memory Map (PGE Package)

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