ADUCM310 datasheet(20/28 Pages) AD

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Data Sheet

ADuCM310

Rev. B Page 19 of 27

Pin No.

Mnemonic

Type1

Description

P0.5/SDA0/PLAO[3]

I/O

General-Purpose Input and Output Port 0.5/I2C Interface Data for

I2C0/Output of PLA Element 3. This pin defaults as an input with internal

pull-up disabled.

P0.6/SCL1/PLAO[4]

I/O

General-Purpose Input and Output Port 0.6/I2C Interface Clock for

I2C1/Output of PLA Element 4. This pin defaults as an input with internal

pull-up disabled.

P0.7/SDA1/PLAO[5]

I/O

General-Purpose Input and Output Port 0.7/I2C Interface Data for

I2C1/Output of PLA Element 5. This pin defaults as an input with internal

pull-up disabled.

P1.0/SIN/ECLKIN/PLAI[4]

I/O

General-Purpose Input and Output Port 1.0/UART Input Pin/External

Input Clock/Input to PLA Element 4. The ECLKIN pin is used for the UART

downloader. This pin defaults as an input with internal pull-up disabled.

P1.1/SOUT/PLACLK1/PLAI[5]

I/O

General-Purpose Input and Output Port 1.1/UART Output Pin/PLA Input

Clock/Input to PLA Element 5. The PLACLK1 pin is used for the UART

downloader. This pin defaults as an input with internal pull-up disabled.

P1.2/PWM0/PLAI[6]

I/O

General-Purpose Input and Output Port 1.2/PWM0 Output/Input to PLA

Element 6. This pin defaults as an input with internal pull-up disabled.

P1.3/PWM1/PLAI[7]

I/O

General-Purpose Input and Output Port 1.3/PWM1 Output/Input to PLA

Element 7. This pin defaults as an input with internal pull-up disabled.

P1.4/PWM2/SCLK1/PLAO[10]

I/O

General-Purpose Input and Output Port 1.4/PWM2 Output/SPI1

Clock/Output of PLA Element 10. This pin defaults as an input with

internal pull-up disabled.

P1.5/PWM3/MISO1/PLAO[11]

I/O

General-Purpose Input and Output Port 1.5/PWM3 Output/SPI1 Data

Master Input-Slave Output/Output of PLA Element 11. This pin defaults as

an input with internal pull-up disabled.

P1.6/PWM4/MOSI1/PLAO[12]

I/O

General-Purpose Input and Output Port 1.6/PWM4 Output/SPI1 Data

Master Output-Slave Input/Output of PLA Element 12. This pin defaults as

an input with internal pull-up disabled.

P1.7/IRQ1/PWM5/CS1/PLAO[13]

I/O

General-Purpose Input and Output Port 1.7/External Interrupt Request 1/

PWM5 Output/SPI1 Chip Select Input/Output of PLA Element 13. This pin

defaults as an input with internal pull-up disabled. If SPI1 is used,

configure this pin as CS1.

P2.0/IRQ2/PWMTRIP/PLACLK2/PLAI[8]

I/O

General-Purpose Input and Output Port 2.0/External Interrupt Request 2/

PWM Trip Input Source/PLA Input Clock/Input to PLA Element 8. This pin

defaults as an input with the internal pull-up disabled.

P2.1/IRQ3/PWMSYNC/PLAI[9]

I/O

General-Purpose Input and Output Port 2.1/External Interrupt Request 3/

PWM Sync Input/Input to PLA Element 9. This pin defaults as an input

with the internal pull-up disabled.

P2.2/IRQ4/MRST/CLKOUT/PLAI[10]

I/O

General-Purpose Input and Output Port 2.2/External Interrupt Request 4/

Reset Out Pin/Clock Output/Input to PLA Element 10. This pin defaults as

an input with the internal pull-up disabled.

P2.3/BM

I/O

General-Purpose Input and Output Port 2.3/BM pin. If this pin is low, then

the device enters UART download after the next rest sequence. This pin

defaults as an input with the internal pull-up disabled.

P2.4/IRQ5/ADCCONV/PWM6/PLAO[18]

I/O

General-Purpose Input and Output Port 2.4/External Interrupt Request 5/

External Input to Start ADC Conversions/PWM6 Output/Output of

PLA Element 18. This pin defaults as an input with the internal pull-up

disabled.

P2.5/IRQ6/PWM7/PLAO[19]

I/O

General-Purpose Input and Output Port 2.5/External Interrupt Request 6/

PWM7 Output/Output of PLA Element 19. This pin defaults as an input

with the internal pull-up disabled.

P2.6/IRQ7/PLAO[20]

I/O

General-Purpose Input and Output Port 2.6/External Interrupt Request 7/

Output of PLA Element 20. This pin defaults as an input with the internal

pull-up disabled.

P2.7/IRQ8/PLAO[21]

I/O

General-Purpose Input and Output Port 2.7/External Interrupt Request 8/

Output of PLA Element 21. This pin defaults as an input with the internal

pull-up disabled.

P3.0/PLAI[12]

I/O

General-Purpose Input and Output Port 3.0/Input to PLA Element 12. This

pin defaults as an input with the internal pull-up disabled.

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