Precision Analog Microcontroller, Tunable

Optical Control Microcontroller

Data Sheet

ADuCM310

Rev. B

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FEATURES

Analog input/output

22-channel, 14-bit, 800 kSPS analog-to-digital

converter (ADC)

10 external channels

1 on-chip die temperature monitor

6 current output digital-to-analog converter (IDAC)

monitor channels

3 power monitor channels

2 buffered reference output channels

Fully differential and single-ended modes

0 V to 2.5 V analog input range

6 low noise, 12-/14-bit IDAC outputs

1× 250 mA, 1× 200 mA, 2× 100 mA, and 2× 20 mA

Semiconductor optical amplifier (SOA) IDAC pull-down

to −3.0 V for fast current sink

Eight 12-bit voltage output DACs (VDACs)

Channel 0 and Channel 1: 0 V to 3 V, 75 Ω load

Channel 2 and Channel 3: −5 V to 0 V, 500 Ω load

Channel 4 and Channel 5: 0 V to 3 V, 300 Ω load

Channel 6: 0 V to 5 V, 500 Ω load

Channel 7: 0 V to 5 V, 100 Ω load

2.5 V, on-chip voltage reference

2 buffered 2.5 V outputs

Microcontroller

ARM Cortex-M3 processor, 32-bit RISC architecture

Serial wire port supports code download and debugging

Clocking options

Trimmed on-chip oscillator (±3%)

80 MHz phase-locked loop (PLL)

External 16 MHz crystal option

External clock source

Memory

2× 128 kB Flash/EE memories, 32 kB SRAM

In-circuit download, SW-DP-based debugging

Software triggered in-circuit reprogrammability

On-chip peripherals

28-pin general-purpose input/output (GPIO) port

3 general-purpose timers

Wake-up (W/U) timer

Watchdog timer (WDT)

32-element programmable logic array (PLA)

Vectored interrupt controller

Interrupt on edge or level external pin inputs

9× external interrupts

Power

Multiple supplies

5 V for VDAC6 and VDAC7

3.3 V for digital and analog inputs/outputs

1.8 V to 2.7 V for IDACs

−5 V supply for IDAC3 and VDAC2/VDAC3

Package and temperature range

6 mm × 6 mm, 112-ball CSP_BGA package

Fully specified for −40°C to +85°C ambient operation

Tools

QuickStart™ development system

Full third party support

APPLICATIONS

Optical modules—tunable laser modules

FUNCTIONAL BLOCK DIAGRAM

RESET

IOVDDx

PVDD_IDACx

AVDDx

DGNDx

SWDIO

SWCLK

PGND

ADuCM310

POR

ON-CHIP

1.8V LDO

32.786kHz

16MHz OSC

80MHz PLL

ARM

CORTEX-M3

PROCESSOR

2.5V BAND

MEMORY

256k FLASH

32k SRAM

DMA

NVIC

PLA

32 × ELEMENTS

GPIO PORTS

UART PORT

2 × SPI PORT

EXT IRQs

3 × GP TIMER

WD TIMER

W/U TIMER

PWM

SERIAL

WIRE

GENERAL-

PURPOSE

I/O PORTS

IDAC

IDAC

BUF

AIN0

AIN9

VDAC

VDAC0

IDAC0

IDAC5

VDAC

VDAC7

14-BIT

SAR

ADC

INTERNAL CHANNELS,

IDACs, TEMPERATURE,

SUPPLIES

MUX

VREF_1.2

BUF_VREF2.5A

BUF_VREF2.5B

Figure 1.