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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ADUCM310 датащи(PDF) 19 Page - Analog Devices |
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ADUCM310 датащи(HTML) 19 Page - Analog Devices |
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19 / 28 page  ADuCM310 Data Sheet Rev. B Page 18 of 27 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RESERVED IDAC0 PVDD_ IDAC0 IDAC2 PVDD_ IDAC2 IDAC3 PGND PVDD_ IDAC3 PVDD_ IDAC1 IDAC1 RESERVED 1 2 3 4 5 6 7 8 9 10 11 1 2 3 4 5 6 7 8 9 10 11 IDAC4 CDAMP_ IDAC0 CDAMP_ IDAC2 IDAC2 PVDD_ IDAC2 IDAC3 PGND PVDD_ IDAC3 CDAMP_ IDAC3 CDAMP_ IDAC1 IDAC5 PVDD_ IDAC4 CDAMP_ IDAC4 P2.3/BM P1.0/ SIN/ ECLKIN/ PLAI[4] P1.2/ PWM0/ PLAI[6] P1.3/ PWM1/ PLAI[7] P1.4/ PWM2/ SCLK1/ PLAO[10] P1.5/ PWM3/ MISO1/ PLAO[11] P1.6/ PWM4/ MOSI1/ PLAO[12] CDAMP_ IDAC5 PVDD_ IDAC5 RESERVED RESET P3.2/ PLAI[14] P2.0/IRQ2/ PWMTRIP/ PLACLK2/ PLAI[8] P1.1/SOUT/ PLACLK1/ PLAI[5] RESERVED P2.4/IRQ5/ ADCCONV/ PWM6/ PLAO[18] P2.5/IRQ6/ PWM7/ PLAO[19] P1.7/IRQ1/ PWM5/CS1/ PLAO[13] DGND2 IREF IOVDD1 P0.1/ MISO0/ PLAI[1] P0.0/ SCLK0/ PLAI[0] P2.2/IRQ4/ MRST/ CLKOUT/ PLAI[10] P2.1/IRQ3/ PWMSYNC/ PLAI[9] SWDIO SWCLK IOVDD2 IOGND1 P0.3/ IRQ0/CS0/ PLAI[3] P0.2/ MOSI0/ PLAI[2] RESERVED ADuCM310 TOP VIEW (Not to Scale) RESERVED VDACVDD AVDD_REG1 IOGND2 P0.7/ SDA1/ PLAO[5] P0.6/ SCL1/ PLAO[4] P0.5/ SDA0/ PLAO[3] P.04/ SCL0/ PLAO[2] AIN4 AGND2 AVDD_REG2 VREF_1.2 P2.6/ IRQ7/ PLAO[20] P2.7/ IRQ8/ PLAO[21] P3.0/ PLAI[12] AGND5 VDAC5 RESERVED AIN1 AIN5 VDAC6 VDAC7 AVDD4 P3.4/ PLAO[26] XTALO P3.1/ PLAI[13] VDAC4 DVDD AIN0 AIN2 AIN6 VDAC2 BUF_ VREF2.5A AGND4 IOVDD3 XTALI DVDD_REG1 VDAC1 AGND1 AVNEG AIN3 AIN7 VDAC3 ADC_CAPN BUF_ VREF2.5B IOGND3 A B C D E F G H J K L IDAC RELATED DIGITAL PINS ANALOG PINS RESERVED A B C D E F G H J K L DGND1 DVDD_REG2 VDAC0 AVDD3 AGND3 AGND6 AIN8 AIN9 ADC_CAPN ADC_CAPP Figure 7. Pin Configuration Table 10. Pin Function Descriptions Pin No. Mnemonic Type1 Description D2 RESET I Reset Input (Active Low). An internal pull-up is included on this pin. E3 P0.0/SCLK0/PLAI[0] I/O General-Purpose Input and Output Port 0.0/SPI0 Clock/Input to PLA Element 0. This pin defaults as an input with the internal pull-up resistor disabled. E2 P0.1/MISO0/PLAI[1] I/O General-Purpose Input and Output Port 0.1/SPI0 Data Master Input-Slave Output/Input to PLA Element 1. This pin defaults as an input with the internal pull-up disabled. F3 P0.2/MOSI0/PLAI[2] I/O General-Purpose Input and Output Port 0.2/SPI0 Data Master Output- Slave Input/Input of PLA Element 2. This pin defaults as an input with the internal pull-up disabled. F2 P0.3/IRQ0/CS0/PLAI[3] I/O General-Purpose Input and Output Port 0.3/External Interrupt Request 0/ SPI0 Chip Select Input/Input of PLA Element 3. This pin defaults as an input with the internal pull-up disabled. If SPI0 is used, configure this pin as CS0. G4 P0.4/SCL0/PLAO[2] I/O General-Purpose Input and Output Port 0.4/I2C Interface Clock for I2C0/Output of PLA Element 2. This pin defaults as an input with the internal pull-up disabled. |
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