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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LTC6915IGN датащи(PDF) 5 Page - Linear Technology |
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LTC6915IGN датащи(HTML) 5 Page - Linear Technology |
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5 / 16 page  LTC6915 5 6915f The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V+ = 5V, V– = –5V, VREF = 0V SHDN and HOLD_THRU Input Current (Note 2) q 5 µA Internal Op Amp Gain Bandwidth 200 kHz Slew Rate 0.2 V/ µs Internal Sampling Frequency 3 kHz Digital I/O, All Digital I/O Voltage Referenced to DGND VIH Digital Input High Voltage q 2.0 V VIL Digital Input Low Voltage q 0.8 V VOH Digital Output High Voltage Sourcing 500 µA q V+ – 0.3 V VOL Digital Output Low Voltage Sinking 500 µA q 0.3 V Digital Input Leakage V+ = 5V, V– = –5V, VIN = 0V to 5V q ±2 µA Timing, V+ = 2.7V to 4.5V, V– = 0V (Note 7) t1 DIN Valid to CLK Setup q 60 ns t2 DIN Valid to CLK Hold q 0ns t3 CLK Low q 100 ns t4 CLK High q 100 ns t5 CS/LD Pulse Width q 60 ns t6 LSB CLK to CS/LD q 60 ns t7 CS/LD Low to CLK q 30 ns t8 DOUT Output Delay CL = 15pF q 125 ns t9 CLK Low to CS/LD Low q 0ns Timing, V+ = 4.5V to 5.5V, V– = 0V (Note 7) t1 DIN Valid to CLK Setup q 30 ns t2 DIN Valid to CLK Hold q 0ns t3 CLK Low q 50 ns t4 CLK High q 50 ns t5 CS/LD Pulse Width q 40 ns t6 LSB CLK to CS/LD q 40 ns t7 CS/LD Low to CLK q 20 ns t8 DOUT Output Delay CL = 15pF q 85 ns t9 CLK Low to CS/LD Low q 0ns Timing, Dual ±4.5V to ±5.5V Supplies (Note 7) t1 DIN Valid to CLK Setup q 30 ns t2 DIN Valid to CLK Hold q 0ns t3 CLK High q 50 ns t4 CLK Low q 50 ns t5 CS/LD Pulse Width q 40 ns t6 LSB CLK to CS/LD q 40 ns t7 CS/LD Low to CLK q 20 ns t8 DOUT Output Delay CL = 15pF q 85 ns t9 CLK Low to CS/LD Low q 0ns |
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