LTC6915IGN datasheet(9/16 Pages) LINER

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LTC6915

6915f

Settling Time vs Gain

Internal Clock Frequency vs

Supply Voltage

GAIN (V/V)

100

1000

10000

6915 G25

VS = 5V

dVOUT = 1V

0.1% ACCURACY

TA = 25°C

SUPPLY VOLTAGE (V)

2.5

10.5

6915 G26

4.5

6.5

8.5

3.40

3.35

3.30

3.25

3.20

3.15

3.10

TA = –55°C

TA = 85°C

TA = 125°C

TA = 25°C

TYPICAL PERFOR A CE CHARACTERISTICS

PI FU CTIO S

IN– (Pin 1/Pin 2): Inverting Analog Input.

SHDN (Pin 1 GN Package Only): Shutdown Pin. The IC is

shut down when SHDN is tied to V+. An internal current

source pulls this pin to V– when floating.

IN+ (Pin 2/Pin 3): Noninverting Analog Input.

V– (Pin 3/Pin 4): Negative Supply.

CS(D0) (Pin 4/Pin 6): TTL Level Input. When in serial

control mode, this pin is the chip select input (active low);

in parallel control mode, this pin is the LSB of the parallel

gain control code.

DIN(D1) (Pin 5/Pin 7): TTL Level Input. When in serial

control mode, this pin is the serial input data; in parallel

mode, this pin is the second LSB of the parallel gain

control code.

HOLD_THRU (Pin 5 GN Package Only): TTL Level Input

for Parallel Control Mode. When HOLD_THRU is high, the

parallel data is latched in an internal D-latch.

CLK(D2) (Pin 6/Pin 8): TTL Level Input. When in serial

control mode, this pin is the clock of the serial interface; in

parallel mode, this pin is the third LSB of the parallel gain

control code.

DOUT(D3) (Pin 7/Pin 9): TTL Level Input. When in serial

control mode, this pin is the output of the serial data; in

parallel mode, this pin is the MSB of the 4-bit parallel gain

(DFN/GN Packages)

control code. In parallel mode operation, if the data in to

DOUT (Pin 9) is from a voltage source greater than V+ (Pin

12), then connect a resistor between the voltage source

and DOUT to limit the current into Pin 9 to 5mA or less.

DGND (Pin 8/Pin 10): Digital Ground.

PARALLEL_SERIAL (Pin 9/Pin 11): Interface Selection

Input. When tied to V+, the interface is in parallel mode, i.e.,

the PGA gain is defined by the parallel codes (D3 ~ D0), i.e.,

CS(D0), DATA(D1), CLK(D2), and DOUT(D3). When

PARALLEL_SERIAL pin is tied to V–, the PGA gain is set

by the serial interface.

REF (Pin 10/Pin 13): Voltage Reference for PGA output.

OUT (Pin 11/Pin 15): Amplifier Output. The typical current

sourcing/sinking of the OUT pin is 1mA. For minimum gain

error, the load resistance should be 1k or greater (refer to

the Output Voltage Swing vs Output Current and Gain

Error vs Load Resistance in the Typical Performance

Characteristics section).

V+ (Pin 12/Pin 16): Positive Supply.

SENSE (Pin 14 GN Package Only): Sense Pin. When the

PGA drives a low resistance load and the interconnect

resistance between the OUT pin and the load is not

negligible, tying the SENSE pin as close as possible to the

load can improve the gain accuracy.

LOAD RESISTANCE RL (k)

0.1

–0.1

–0.2

–0.3

–0.4

6915 G27

AV = 4096

AV = 256

AV = 16

Additional Gain Error vs Load

Resistance

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