AD5522JSVDZ datasheet(11/65 Pages) AD

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AD5522

Data Sheet

Rev. E | Page 10 of 64

Parameter

Min

Typ 1

Max

Unit

Test Conditions/Comments

DIE TEMPERATURE SENSOR

Accuracy2

±7

°C

Output Voltage at 25°C

1.5

Output Scale Factor2

4.6

mV/°C

Output Voltage Range2

INTERACTION AND CROSSTALK2

DC Crosstalk (FOHx)

0.05

0.65

DC change resulting from a dc change in any DAC

in the device, FV and FI modes, ±2 mA range,

CLOAD = 200 pF, RLOAD = 5.6 kΩ

DC Crosstalk (MEASOUTx)

0.05

0.65

DC change resulting from a dc change in any DAC

in the device, MV and MI modes, ±2 mA range,

CLOAD = 200 pF, RLOAD = 5.6 kΩ

DC Crosstalk Within a Channel

0.05

All channels in FVMI mode, one channel at midscale;

measure the current for one channel in the lowest

current range for a change in comparator or clamp

DAC levels for that PMU

SPI INTERFACE LOGIC INPUTS

Input High Voltage, VIH

1.7/2.0

(2.3 V to 2.7 V)/(2.7 V to 5.25 V), JEDEC-compliant

input levels

Input Low Voltage, VIL

0.7/0.8

(2.3 V to 2.7 V)/(2.7 V to 5.25 V), JEDEC-compliant

input levels

Input Current, IINH, IINL

−1

µA

Input Capacitance, CIN2

CMOS LOGIC OUTPUTS

SDO, CPOx

Output High Voltage, VOH

DVCC − 0.4

Output Low Voltage, VOL

0.4

IOL = 500 µA

Tristate Leakage Current

−2

µA

SDO, CPOH1/SDO

−1

µA

All other output pins

Output Capacitance2

OPEN-DRAIN LOGIC OUTPUTS

BUSY, TMPALM, CGALM

Output Low Voltage, VOL

0.4

IOL = 500 µA, CLOAD = 50 pF, RPULLUP = 1 kΩ

Output Capacitance2

LVDS INTERFACE LOGIC INPUTS

REDUCED RANGE LINK2

Input Voltage Range

875

1575

Input Differential Threshold

−100

+100

External Termination Resistance

100

120

Differential Input Voltage

100

LVDS INTERFACE LOGIC OUTPUTS

REDUCED RANGE LINK

Output Offset Voltage

1200

Output Differential Voltage

400

POWER SUPPLIES

AVDD

|AVDD − AVSS| ≤ 33 V

AVSS

−23

−5

DVCC

2.3

5.25

AIDD

Internal ranges (±5 μA to ±2 mA), excluding load

conditions; comparators and guard disabled

AISS

−26

Internal ranges (±5 μA to ±2 mA), excluding load

conditions; comparators and guard disabled

AIDD

Internal ranges (±5 μA to ±2 mA), excluding load

conditions; comparators and guard enabled

AISS

−28

Internal ranges (±5 μA to ±2 mA), excluding load

conditions; comparators and guard enabled

AIDD

External range, excluding load conditions

AISS

−36

External range, excluding load conditions

DICC

1.5

Maximum Power Dissipation2

Maximum power that should be dissipated in this

package under worst-case load conditions; careful

consideration should be given to supply selection

and thermal design

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