AD5522JSVDZ datasheet(54/65 Pages) AD

54 / 65 page

Data Sheet

AD5522

Rev. E | Page 53 of 64

READ REGISTERS

Readback of all the registers in the device is possible via the SPI

and the LVDS interfaces. To read data from a register, it is first

necessary to write a readback command to tell the device which

appropriate channel.

When the required channel is addressed, the device loads

the 24-bit readback data into the MSB positions of the 29-bit

serial shift register (the five LSBs are filled with 0s). SCLK rising

edges clock this readback data out on SDO (framed by the

SYNC signal).

A minimum of 24 clock rising edges is required to shift the

readback data out of the shift register. If writing a 24-bit word to

shift data out of the device, the user must ensure that the 24-bit

write is effectively an NOP (no operation) command. The last

five bits in the shift register are always 00000: these five bits

become the MSBs of the shift register when the 24-bit write is

loaded. To ensure that the device receives an NOP command as

described in Table 20, the recommended flush command is

0xFFFFFF; thus, no change is made to any register in the device.

Readback data can also be shifted out by writing another 29-bit

write or read command. If writing a 29-bit command, the read-

back data is MSB data available on SDO, followed by 00000.

Table 30. Read Functions of the AD5522

B28

B27

B26

B25

B24

B23

B22

B21 to B0

Selected Channel

RD/WR

PMU3

PMU2

PMU1

PMU0

MODE1

MODE0

Data bits

CH3

CH2

CH1

CH0

Read Functions

All 0s

Read from system control register

All 0s

Read from comparator status register

X (don’t care)

Reserved

All 0s

Read from alarm status register

Read Addressed PMU Register (Only One PMU Register Can Be Read at One Time)

All 0s

CH0

CH1

CH2

CH3

Read Addressed DAC M Register (Only One DAC Register Can Be Read at One Time)

DAC address

(see Table 29)

CH0

CH1

CH2

CH3

Read Addressed DAC C Register (Only One DAC Register Can Be Read at One Time)

DAC address

(see Table 29)

CH0

CH1

CH2

CH3

Read Addressed DAC X1 Register (Only One DAC Register Can Be Read at One Time)

DAC address

(see Table 29)

CH0

CH1

CH2

CH3

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