HT36A2 datasheet(11/24 Pages) HOLTEK

11 / 24 page

HT36A2

Rev. 1.00

June 19, 2003

with pull-high resistor, which can be used to synchronize

external logic. The RC oscillator provides the most cost

effective solution. However, the frequency of the oscilla-

tion may vary with VDD, temperature, and the chip itself

due to process variations. It is therefore, not suitable for

timing sensitive operations where accurate oscillator

frequency is desired.

On the other hand, if the crystal oscillator is selected, a

crystal across OSC1 and OSC2 is needed to provide the

feedback and phase shift required for the oscillator, and

no other external components are required. A resonator

may be connected between OSC1 and OSC2 to replace

the crystal and to get a frequency reference, but two ex-

ternal capacitors in OSC1 and OSC2 are required.

The WDT oscillator is a free running on-chip RC oscilla-

tor, and no external components are required. Even if

the system enters the power down mode, the system

clock is stopped, but the WDT oscillator still works with a

period of approximately 78

ms. The WDT oscillator can

be disabled by mask option to conserve power.

Watchdog Timer

- WDT

The WDT clock source is implemented by a dedicated

RC oscillator (WDT oscillator) or instruction clock (sys-

tem clock of the MCU divided by 4), determined by mask

options. This timer is designed to prevent a software

malfunction or sequence jumping to an unknown loca-

tion with unpredictable results. The Watchdog Timer can

be disabled by mask option. If the Watchdog Timer is

disabled, all the executions related to the WDT result in

no operation.

Once the internal WDT oscillator (RC oscillator with a

period of 78

ms normally) is selected, it is first divided by

256 (8-stages) to get the nominal time-out period of ap-

proximately 20ms. This time-out period may vary with

temperature, VDD and process variations. By invoking

the WDT prescaler, longer time-out periods can be real-

ized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the

WDTS) can give different time-out periods. If WS2,

WS1, WS0 all equal to 1, the division ratio is up to 1:128,

and the maximum time-out period is 2.6 seconds.

If the WDT oscillator is disabled, the WDT clock may still

come from the instruction clock and operate in the same

manner except that in the HALT state the WDT may stop

counting and lose its protecting purpose. In this situation

the logic can only be restarted by external logic. The

high nibble and bit 3 of the WDTS are reserved for user

defined flags, and the programmer may use these flags

to indicate some specified status.

WS2

WS1

WS0

Division Ratio

000

1:1

001

1:2

010

1:4

011

1:8

1:16

1:32

1:64

1:128

If the device operates in a noisy environment, using the

on-chip RC oscillator (WDT OSC) is strongly recom-

mended, since the HALT will stop the system clock.

The WDT overflow under normal operation will initialize

²chip reset² and set the status bit TO. Whereas in the

HALT mode, the overflow will initialize a

²warm reset²

only the PC and SP are reset to zero. To clear the WDT

contents (including the WDT prescaler ), 3 methods are

implemented; external reset (a low level to RES), soft-

ware instructions, or a HALT instruction. The software

instructions include CLR WDT and the other set

- CLR

WDT1 and CLR WDT2. Of these two types of instruc-

tions, only one can be active depending on the mask op-

tion

-²CLR WDT times selection option².Ifthe ²CLR

WDT

² is selected (i.e. CLRWDT times equal one), any

execution of the CLR WDT instruction will clear the

WDT. In case

²CLR WDT1² and ²CLR WDT2² are cho-

sen (i.e. CLRWDT times equal two), these two instruc-

tions must be executed to clear the WDT; otherwise, the

WDT may reset the chip because of time-out.

C r y s t a l O s c i l l a t o r

R C O s c i l l a t o r

O S C 1

O S C 2

f S Y S / 8

O S C 1

V D D

System oscillator

S y s t e m C l o c k / 8

8 - b i t C o u n t e r

W D T P r e s c a l e r

7 - b i t C o u n t e r

8 - t o - 1 M U X

W D T T i m e - o u t

W S 0 ~ W S 2

M a s k

O p t i o n

S e l e c t

W D T

O S C

Watchdog timer

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