PCF2113X datasheet(41/72 Pages) PHILIPS

41 / 72 page

2001 Dec 19

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2113x

14 AC CHARACTERISTICS

VDD1 = 1.8 to 5.5 V; VDD2 =VDD3 = 2.2 to 4.0 V; VSS =0V;VLCD = 2.2 to 6.5 V; Tamb = −40 to +85 °C; unless otherwise

speciﬁed.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

fFR

LCD frame frequency (internal clock)

VDD = 5.0 V

147

fosc

oscillator frequency (not available at any pin)

140

250

450

kHz

fOSC(ext)

external clock frequency

140

−

450

kHz

tosc(st)

oscillator start-up time after power-down

note 1

−

200

300

µs

tW(PD)

power-down HIGH-level pulse width

−−µs

tSW(PD)

tolerable spike width on PD pin

note 1

−−

Timing characteristics of parallel interface; note 2

WRITE OPERATION (WRITING DATA FROM MICROCONTROLLER TO PCF2113X); see Fig.27

Tcy(en)

enable cycle time

500

−−

tW(en)

enable pulse width

220

−−

tsu(A)

address set-up time

−−

th(A)

address hold time

−−

tsu(D)

data set-up time

−−

th(D)

data hold time

−−

READ OPERATION (READING DATA FROM PCF2113X TO MICROCONTROLLER); see Fig.28

Tcy(en)

enable cycle time

500

−−

tW(en)

enable pulse width

220

−−

tsu(A)

address set-up time

−−

th(A)

address hold time

−−

td(D)

data delay time

VDD1 > 2.2 V

−−

150

VDD1 > 1.5 V

−−

250

th(D)

data hold time

−

100

Timing characteristics of I2C-bus interface; see Fig.29; note 2

fSCL

SCL clock frequency

−−

400

kHz

tLOW

SCL clock LOW period

1.3

−−µs

tHIGH

SCL clock HIGH period

0.6

−−µs

tSU;DAT

data set-up time

100

−−

tHD;DAT

data hold time

−−

SCL and SDA rise time

note 1 and 3

15 + 0.1 Cb

−

300

SCL and SDA fall time

note 1 and 3

15 + 0.1 Cb

−

300

capacitive bus line load

−−

400

tSU;STA

set-up time for a repeated START condition

0.6

−−µs

tHD;STA

START condition hold time

0.6

−−µs

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