AD9260ASZ datasheet(26/45 Pages) AD

26 / 45 page

AD9260

Rev. C | Page 25 of 44

ANALOG

MODULATOR

VINA

VINB

SS1

SS2

CS1

CS2

SS3

SH1

SS4

SH2

SH3

SH4

CPB1

CPB2

CPA1

CPA2

Figure 61. Detailed Analog Input Structure

Figure 61 illustrates the analog input structure of the AD9260.

For the moment, ignore the presence of the parasitic capacitors

CPA and CPB. The effects of these parasitic capacitors will be

discussed near the end of this section. The switched capacitors,

CS1 and CS2, sample the input voltages applied on pins VINA

and VINB. These capacitors are connected to input pins VINA

and VINB when CLK is low. When CLK rises, a sample of the

input signal is taken on capacitors CS1 and CS2. When CLK is

high, capacitors CS1 and CS2 are connected to the Analog

Modulator. The modulator precharges capacitors CS1 and CS2

to minimize the amount of charge required from any circuit

used in combination with the AD9260 to drive input pins VINA

and VINB. This reduces the input drive requirements of the

analog circuitry driving pins VINA and VINB. The Analog

Modulator precharges the voltages across capacitors CS1 and

CS2, approximately equal to a delayed version of the input

signal. When capacitors CS1 and CS2 are connected to input

pins VINA and VINB, the differential charge, Q(n), on these

capacitors is given in the following equation,

VCORE

−

)

(

(6)

where q1 and q2 are the individual charges stored on capacitors

CS1 and CS2 respectively, and CS is the capacitance value of

CS1 and CS2. When capacitors CS1 and CS2 are connected to

the Analog Modulator during the preceding precharge clock

phase, the capacitors are precharged equal to an approximation

of a previous sample of the input signal. Consequently the

differential charge on these capacitors while CLK is high is

given in the following equation,

()

Vdelta

delay

VCORE

− )

(

(7)

where VCORE(delay) is the value of VCORE sampled during a

previous period of CLK, and Vdelta is the sigma-delta error

voltage left on the capacitors. Vdelta is a natural artifact of the

sigma-delta feedback techniques utilized in the Analog

Modulator of the AD9260. It is a small random voltage term

that changes every clock period and varies from 0 to ±0.05

×VREF.

The analog circuitry used to drive the input pins of the AD9260

must respond to the charge glitch that occurs when capacitors

CS1 and CS2 are connected to input pins VINA and VINB. This

circuitry must provide additional charge, qdelta, to capacitors

CS1 and CS2, which is the difference between the precharged

value, Q(n–1), and the new value, Q(n), as given in the

following equation,

( )

(

)

−

Qdelta

(8)

()

[

]

Vdelta

delay

VCORE

Qdelta

−

(9)

DRIVING THE INPUT

Transient Response

The charge glitch occurs once at the beginning of every period

of the input CLK (falling edge), and the sample is taken on

capacitors CS1 and CS2 exactly one-half period later (rising

edge). Figure 62 presents a typical input waveform applied to

input Pins VINA and VINB of the AD9260.

CLOCK

VINA-VINB

TRACK SAMPLE TRACK SAMPLE TRACK SAMPLE TRACK SAMPLE

Figure 62. Typical Input Waveform

Figure 62 illustrates the effect of the charge glitch when a source

with nonzero output impedance is used to drive the input pins.

This source must be capable of settling from the charge glitch in

one-half period of the CLK. Unfortunately, the MOS switches

used in any CMOS-switched capacitor circuit (including those

in the AD9260) include nonlinear parasitic junction

capacitances connected to their terminals. Figure 61 also

illustrates the parasitic capacitances, Cpa1, Cpb1, Cpa2, and

Cpb2, associated with the input switches.

Parasitic capacitor Cpa1 and Cpa2 are always connected to Pins

VINA and VINB and therefore do not contribute to the glitch

energy. Parasitic capacitors Cpb1 and Cpb2, on the other hand,

cause a charge glitch that adds to that of input capacitors CS1

and CS2 when they are connected to input Pins VINA and

VINB. The nonlinear junction capacitance of Cpb1 and Cpb2

cause charge glitch energy that is nonlinearily related to the

input signal. Therefore, linear settling is difficult to achieve

unless the input source completely settles during one-half

period of CLK. A portion of the glitch impulse energy kicked

back at the source is not linearly related to the input signal.

Therefore, the best way to ensure that the input signal settles

linearly is to use wide bandwidth circuitry, which settles as

completely as possible from the glitch during one-half period of

the CLK.

The AD9260 utilizes a proprietary clock-boosted boot-

strapping technique to reduce the nonlinear parasitic

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