AD9260ASZ datasheet(37/45 Pages) AD

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AD9260

Rev. C | Page 36 of 44

EVALUATION BOARD GENERAL DESCRIPTION

The AD9260 Evaluation Board is designed to provide an easy

and flexible method of exercising the AD9260 and demonstrate

its performance to data sheet specifications. The evaluation

board is fabricated in four layers: the component layer, the

ground layer, the power layer, and the solder layer. The board is

clearly labeled to provide easy identification of components.

Ample space is provided near the analog and clock inputs to

provide additional or alternate signal conditioning.

FEATURES AND USER CONTROLS

Jumper Controlled Mode/OSR Selection

The choice of Mode/OSR can easily be varied by jumping either

JP1, JP2, JP3, or JP4 as illustrated in Figure 78 within the

Mode/OSR Control Block. To obtain the desired mode, refer to

Table 16.

Table 16. AD9260 Evaluation Board Mode Select

Mode/OSR

Connect Jumper

1×

JP4

2×

JP2

4×

JP3

8×

JP1

Selectable Power Bias

The power consumption of the AD9260 can be scaled down if

the user is able to operate the device at a lower clock frequency.

As illustrated in Figure 78, pin cups are provided for the

external resistor (R2) tied to the BIAS pin of the AD9260.

Table 17 defines the recommended resistance for a given clock

speed to obtain the desired power consumption.

Table 17. Evaluation Board Recommended Resistance Value

for External Bias Resistor

Resistor Value

Clock Speed (max)

Power Consumption

2 kΩ

20 MHz

585 mW

4 kΩ

10 MHz

325 mW

8 kΩ

5 MHz

200 mW

16 kΩ

2.5 MHz

150 mW

Data Interfacing Controls

The data interfacing controls (RESETB, CSB, READ, DAV) are

all accessible via SMA connectors (J2–J5) as illustrated in

Figure 78 within the data interfacing control block. The

RESETB, CSB, and READ connections are each supplied with

two sets or resistor pin cups to allow the user to pull-up or pull-

down each signal to a fixed state. R5, R6, and R30 will terminate

to ground, while R7, R28, and R29 terminate to DRVDD. The

DAV and OTR signals are also directly connected to the data

output connector P1. All interfacing controls are buffered

through the CMOS line driver 74HC541.

Buffered Output Data

The twos complement output data is buffered through two

CMOS noninverting bus transceivers (U2 and U3) and made

available at pin connector P1 as illustrated in Figure 78 within

the data output block.

Jumper Controlled Reference Source

The choice of reference for the AD9260 can easily be varied

between 1.0 V, 2.5 V or external by using jumpers JP5, JP6, JP7,

and JP9 as illustrated in Figure 78 within the reference

configuration block. To obtain the desired reference, see

Table 18.

AD817R

C15

0.1

µF

C17

µF

R11

49.9

Ω

JP10

R12

15k

Ω

R13

10k

Ω

15k

Ω

10k

Ω

R10

Ω

VCC2

C14

390

Ω

2N2222

C12

C13

µF

2.5/3V

VOUT

TRIM

+VIN

TEMP

GNDS

AD780R

C18

0.1

µF

0.1

µF

0.1

µF

0.1

µF

C19

VCC2

AGND

VREFEXT

1KPOT

Figure 77. Evaluation Board External Reference Circuitry

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