Description
The TC518129B-V is a 1M bit high speed CMOS pseudo static RAM organized as 131,072 words by 8 bits. The TC518129B-V
utilizes a one transistor dynamic memory cell with CMOS peripheral circuitry to provide high capacity, high speed and low power
storage. The TC518129B-V operates from a single power supply of 2.7-5.5V. Refreshing is supported by a refresh (RFSH) input
which enables two types of refreshing - auto refresh and self refresh. The TC518129B-V features a static RAM-like interface with a
write cycle in which the input data is written into the memory cell at the rising edge of R/W thus simplifying the microprocessor
interface.
A CS standby mode interface is incorporated in the TC518129B-V family, with the CE2 pin in the TC518128B-V family changed
to a CS pin. The TC518129B-V is available in a 32-pin, 0.6 inch width plastic DIP, a small outline plastic flat package, and a 32-pin thin
small outline plastic package (forward type).

Features
•
Organization:
• Low voltage operation:
• Data retention supply voltage:
• Fast access time
ICEA CE Access Time
TOEA OE Access Time
tac Cycle Time
Power Dissipation
Self Refresh Current
5.5V
3.0V
131,072 words x 8 bits
2.7V-5.5V
2.7V - 5.5V
TC518129B-V Family
-70
70ns
25ns
115ns
385mW
-80
80ns
30ns
130ns
330mW
50μA
25μA
Auto refresh is supported by an internal refresh address
counter
Self refresh is supported by an internal timer
Inputs and outputs TTL compatible
Refresh: 512 refresh cycles/8ms
• Auto refresh power down feature
Package
- TC518129BPL-V: DIP32-P-600
- TC518129BFL-V: SOP32-P-450
- TC518129BFWL-V: SOP32-P-525
- TC518129BFTL-V: TSOP32-P-0820
-10
100ns
40ns
160ns
275mW