DESCRIPTION
The TC518128CPL/CSPL/CFL/CFWL/CFTL is a 1,048,578-bit CMOS pseudo static random access memory
(PSRAM) organized as 131,072 words by 8 bits. It feature a one-transistor dynamic memory cell using CMOS
peripheral circuitry to provide large capacity, high speed and low power. It uses a single 5 V ± 10% power
supply. A RFSH input selects either auto or self refresh operation. This device family also features SRAM-like
write functions whereby data is written to the memory cell rising edge of R/W signal, for easy interfacing to
microprocessors. The TC518128CPL/CSPL/CFL/CFWL/CFTL meets the JEDEC CMOS SRAM pin-
compatibility standard and is available in molded 32-pin standard 0.6-inch and 0.3-inch dual-inline plastic
packages (DIP) and 0.45-inch and 0.525-inch small-outline plastic packages (SOP), and thin small-outline
plastic package (TSOP).

FEATURES
Organized as 131,072 words by 8 bits
(1,048,576 bits).
Fast access time and low power dissipation.
Single power supply voltage of 5 V ± 10%.
TC518128C Family
tCEA CE Access Time
TOEA OE Access Time
tec Cycle Time
Power Dissipation
Self Refresh Current
-70
70 ns
25 ns
115 ns
385 mW
-80
80 ns
30 ns
130 ns
-10
100 ns
40 ns
160 ns
275 mW
330 mW
100A (L version)
50 μA (LL version)

Internal counter can be used for auto and self refresh
operations.
• Internal timer can be used for self refresh operation.
• Auto refresh power down function.
• 512 refresh cycles per 8 ms.
• All inputs and outputs are TTL compatible.
● Pin compatible with 1M SRAM (JEDEC).
• Logic compatible with SRAM R/W pin.
Packages:
DIP32-P-600-2.54 (CPL)
SOP32-P-450-1.27 (CFL)
DIP32-P-300-2.54 (CSPL)
SOP32-P-525-1.27 (CFWL)
TSOP I 32-P-0820-0.50 (CFTL)
(Weight: 4.45 g typ)
(Weight: 2.34 g typ)
(Weight: 0.86 g typ)
(Weight: 1.04 g typ)
(Weight: 0.32 g typ)