AD7667AST datasheet(22/29 Pages) AD

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AD7667

Rev. 0 | Page 21 of 28

CONVERSION CONTROL

Figure 33 shows the detailed timing diagrams of the conversion

process. The AD7667 is controlled by the CNVST signal, which

initiates conversion. Once initiated, it cannot be restarted or

aborted, even by the power-down input PD, until the conversion

is complete. CNVST operates independently of CS and RD.

In Impulse mode, conversions can be automatically initiated. If

CNVST is held LOW when BUSY is LOW, the AD7667 controls

the acquisition phase and automatically initiates a new con-

version. By keeping CNVST LOW, the AD7667 keeps the

conversion process running by itself. It should be noted that the

analog input must be settled when BUSY goes LOW. Also, at

power-up, CNVST should be brought LOW once to initiate the

conversion process. In this mode, the AD7667 can run slightly

faster than the guaranteed 666 kSPS limits in Impulse mode.

This feature does not exist in Warp and Normal modes.

Although CNVST is a digital signal, it should be designed with

special care with fast, clean edges, and levels with minimum

overshoot and undershoot or ringing.

The CNVST trace should be shielded with ground and a low

value serial resistor (e.g., 50 Ω) termination should be added

close to the output of the component that drives this line.

For applications where SNR is critical, the CNVST signal should

have very low jitter. This can be achieved by using a dedicated

oscillator for CNVST generation, or by clocking CNVST with a

high frequency, low jitter clock, as shown in Figure 26.

BUSY

MODE

ACQUIRE

CONVERT

ACQUIRE

CONVERT

CNVST

Figure 33. Basic Conversion Timing

RESET

DATA

BUSY

CNVST

Figure 34. RESET Timing

t11

BUSY

DATA

BUS

CS = RD = 0

t10

PREVIOUS CONVERSION DATA

NEW DATA

CNVST

Figure 35. Master Parallel Data Timing for Reading (Continuous Read)

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