CY29352
Document #: 38-07476 Rev. **
Page 2 of 8
Pin Description[1]
Pin
Name
I/O
Type
Description
6
REFCLK
I, PD
LVCMOS
Reference clock input.
12, 14, 15,
18, 19
QA(0:4)
O
LVCMOS
Clock output bank A.
22, 23, 26, 27 QB(0:3)
O
LVCMOS
Clock output bank B.
30, 31
QC(0,1)
O
LVCMOS
Clock output bank C.
8
FB_IN
I, PD
LVCMOS
Feedback clock input. Connect to an output for normal operation. This
input should be at the same voltage rail as input reference clock. See
Table 1.
1
VCO_SEL
I, PD
LVCMOS
VCO divider select input. See Table 2.
5MR/OE#
I, PD
LVCMOS
Master reset/output enable/disable input. See Table 2.
9
PLL_EN#
I, PD
LVCMOS
PLL enable/disable input. See Table 2.
2, 3, 4
SEL(A:C)
I, PD
LVCMOS
Frequency select input, Bank (A:C). See Table 2.
16, 20
VDDQA
Supply
VDD
2.5V or 3.3V power supply for bank A output clocks.[2,3]
21, 25
VDDQB
Supply
VDD
2.5V or 3.3V power supply for bank B output clocks.[2,3]
32
VDDQC
Supply
VDD
2.5V or 3.3V power supply for bank C output clocks.[2,3]
10
AVDD
Supply
VDD
2.5V or 3.3V power supply for PLL.[2,3]
11
VDD
Supply
VDD
2.5V or 3.3V power supply for core and inputs.[2,3]
7AVSS
Supply
Ground
Analog ground.
13, 17, 24,
28, 29
VSS
Supply
Ground
Common ground.
Table 1. Frequency Table
VCO_SEL
Feedback Output
Divider
VCO
Input Frequency Range
(AVDD = 3.3V)
Input Frequency Range
(AVDD = 2.5V)
0
÷2
Input Clock * 2
100 MHz to 200 MHz
100 MHz to 200 MHz
0
÷4
Input Clock * 4
50 MHz to 125 MHz
50 MHz to 100 MHz
0
÷6
Input Clock * 6
33.33 MHz to 83.33 MHz
33.33 MHz to 66.67 MHz
1
÷2
Input Clock * 4
50 MHz to 125 MHz
50 MHz to 100 MHz
1
÷4
Input Clock * 8
25 MHz to 62.5 MHz
25 MHz to 50 MHz
1
÷6
Input Clock * 12
16.67 MHz to 41.67 MHz
16.67 MHz to 33.33 MHz
Table 2. Function Table
Control
Default
0
1
VCO_SEL
0
VCO
VCO
÷ 2
PLL_EN#
0
PLL enabled. The VCO output connects
to the output dividers
Bypass mode, PLL disabled. The input clock
connects to the output dividers
MR/OE#
0
Outputs enabled
Outputs disabled (three-state), VCO running at
its minimum frequency
SELA
0
QA = VCO
÷ 4
QA = VCO
÷ 6
SELB
0
QB = VCO
÷ 4
QB = VCO
÷ 2
SELC
0
QC = VCO
÷ 2QC = VCO ÷ 4
Notes:
1.
PD = Internal pull-down.
2.
A 0.1-
µF bypass capacitor should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins their
high frequency filtering characteristics will be cancelled by the lead inductance of the traces.
3.
AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, and VDDQC power supply pins.
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