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CY29352
Document #: 38-07476 Rev. **
Page 4 of 8
AC Parameters[6] (VDD= 2.5V ± 5%, TA = –40°C to +85°C)
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
fVCO
VCO Frequency
200
400
MHz
fin
Input Frequency
÷2 Feedback
100
200
MHz
÷4 Feedback
50
100
÷6 Feedback
33.33
66.67
÷8 Feedback
25
50
÷12 Feedback
16.67
33.33
Bypass mode (PLL_EN# = 1)
0
200
frefDC
Input Duty Cycle
25
75
%
tr , tf
TCLK Input Rise/FallTime
0.7V to 1.7V
1.0
ns
fMAX
Maximum Output Frequency
÷2 Output
100
200
MHz
÷4 Output
50
100
÷6 Output
33.33
66.67
÷8 Output
25
50
÷12 Output
16.67
33.33
DC
Output Duty Cycle
fMAX < 100 MHz
47
53
%
fMAX > 100 MHz
44
56
tr , tf
Output Rise/Fall times
0.6V to 1.8V
0.1
1.0
ns
t(φ)
Propagation Delay (static phase
offset)
TCLK to FB_IN, same VDD,
does not include jitter
-100
100
ps
tsk(O)
Output-to-Output Skew
Skew within Bank
125
ps
tsk(B)
Bank-to-Bank Skew
Banks at same voltage, same
frequency
175
ps
Banks at same voltage,
different frequency
225
tPLZ, HZ
Output Disable Time
8
ns
tPZL, ZH
Output Enable Time
10
ns
BW
PLL Closed Loop Bandwidth (-3dB)
÷2 Feedback
2
MHz
÷4 Feedback
1 - 1.5
÷6 Feedback
0.6
÷8 Feedback
0.75
÷12 Feedback
0.5
tJIT(CC)
Cycle-to-Cycle Jitter
Same frequency
100
ps
Multiple frequencies
300
tJIT(PER)
Period Jitter
Same frequency
100
ps
Multiple frequencies
150
tJIT(φ)
I/O Phase Jitter
VCO < 300 MHz
150
ps
VCO > 300 MHz
100
tLOCK
Maximum PLL Lock Time
1
ms
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