MFC2000 datasheet(192/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

7-44

Conexant

100723A

Clock Stretching

Slave can add wait state as needed by stretching the low period of the clock. This will slow down the bus as

shown below.

Master's SIC

Slave's SIC

SIC

wait state

Figure 7-26. Stretching the Low Period of the Clock

7.2.2

Name/Address

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default

SPI Control

(SPICtrl)

$01FF854B

(Not Used)

WRI

(read only)

Rst. Value

xxxxxxx0b

Read Value

00h

Name/Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

SPI Control

(SPICtrl)

$01FF854A

RST

REA

STA

STO

RAC

WAC

SID

SIC

Rst. Value

00h

Read Value

00h

Bit 8

WRI – Writing

This is a read only bit which indicates the writing operation. Reading a

means the SPI is in the process of sending/writing data to slave.

Bit 7

RST – Reset

Writing a 1 to this bit will cause the SPI logic controller to be resetted.

If SPI is in operation while RST bit is set, then the operation will be

terminated. Reading a 1 from this bit indicates that RST operation is

active. After the reset, both SID and SIC lines will be released.

Bit 6

REA – Read

Writing a 1 to this bit will generate 8 clocks to read data from slave,

and SPI will capture serial data into the upper byte of ‘SPI_data’

active.

Bit 5

STA – Start

Writing a 1 to this bit will generate START condition. Reading a 1 from

this bit indicates STA operation is active.

Bit 4

STO – Stop

Writing a 1 to this bit will generate STOP condition. Reading a 1 from

this bit indicates STO operation is active.

Bit 3

RAC – Read Acknowledge

Writing a 1 to this bit will generate ACKNOWLEDGE condition after

read operation in which the master will:

1. generate clock pulse

2. drive SID low

Reading a 1 from this bit indicates RAC operation is active.

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