MFC2000 datasheet(135/426 Pages) ETC

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Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

5-9

Bit 2:

Bank 0 Enable

This bit controls whether or not the Bank 0 DRAMs will be enabled.

The Enable signal will allow CAS before RAS refresh to occur based

on the non-interleave or interleave setting. If the bank setting indicates

a non-interleaved mode, RASn[0] and CASOn[0] (8-bit mode) or

CASOn[1:0] (16-bit mode) will refresh the DRAM. If the bank setting

indicates an interleaved mode, RASn[0], CASOn[1:0] and CASEn[1:0]

will refresh the DRAM. DWRn will be high during refresh. CASEn[1:0]

will be tristated if Bank 1 is in non-interleaved mode. If this bit is set to

a zero, RASn[0] will be tristated. Default disabled.

Bit 1:

Bank 1 Interleave Enable

This register defines whether the bank 1 DRAMs are to be accessed

using 2-way interleave or non-interleaved access. 2-way interleaved

access is only valid with a 16-bit interface (the 16 bit vs. 8 bit interface

size bit for bank 1 is not used by the DRAM controller in the interleave

mode, but is used by the SIU to output the data correctly).

Bit 0:

Bank 0 Interleave Enable

This register defines whether the bank 0 DRAMs are to be accessed

using 2-way interleave or non-interleaved access. 2-way interleaved

access is only valid with a 16-bit interface (the 16 bit vs. 8 bit interface

size bit for bank 1 is not used by the DRAM controller in the interleave

mode, but is used by the SIU to output the data correctly).

Address

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default

Lock Enable

(LockEnn)

01FF80A1(DW)

A Dummy write to the Lock Enable register will enable the battery/prime power lockout sequence for a power

down condition.

Rst. Value

xxh

Read Value

xxh

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

Lock Enable

(LockEnn)

01FF80A0 (DW)

A Dummy write to the Lock Enable register will enable the battery/prime power lockout sequence for a power

down condition.

Rst. Value

xxh

Read Value

xxh

• A write to this register enables the battery power lockout sequence for a power down condition. Lockout can

only be cleared by resn.

• This is not a battery backed-up register.

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