MFC2000 datasheet(130/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

5-4

Conexant

100723A

VDD Power On

VDD power on occurs when VDD power reaches it's normal operating level and PWRDWNn is driven high,

resulting in “Power-Up Delay 1” (PUD1) initiation (shown at upper left in Figure 5-1). PUD1 has a duration of one

or two Reset clocks (internal signal), depending on when PWRDWNn is driven high with respect to the Reset

clock rising edge. Once PUD1 times out, the internal signal Battrtc_RESn is released. The internal Reset clock

signal (RESn) duration is equal to approximately 125 ms for XOUT = 32.768 kHz.

Reset clock = XOUT/4096

“Power-Up Delay 2” (PUD2) is a time delay whose duration is approximately 8 periods of SIUCLK (6 SIUCLK

periods + time for retiming to AUXCLK). This delay allows CPU pre-operation initialization. Once PUD2 times out,

RESETn gets resynchronized to AUXCLK and then, changes from an active low state to a high impedance state.

After RESETn goes to the high impedance state, RESn goes high approximately after 8 periods of SIUCLK. After

the internal RESn signal goes high, all internal logic gets reset and the battery back-up lockout is removed on the

next XOUT rising edge.

VDD Power Off

VDD power off occurs when PWRDWNn is driven low while VDD is at a normal operating level. As an MFC2000

battery backed up feature, PWRDWNn has been designed to work with an early warning power loss detector.

This allows the firmware to backup sensitive variables, and the MFC2000 to protect nonvolatile data from

erroneous logic operations while prime power transitions through low voltage levels (i.e., < 3.135V).

When PWRDWNn is driven low, an SYSIRQ is issued to the CPU, and the CPU SYSIRQ routine then performs

necessary system house cleaning tasks before power loss. The final SYSIRQ routine task is to write to the

LockEnn register, which enables the battery lockout logic. The battery lockout logic forces an immediate lockout if

battery DRAM operation is not enabled. If DRAM operation is enabled, the battery lockout logic waits for the

absence of a VDD refresh cycle before performing the lockout. While in lockout, battery refresh mode

commences, Battrtc_RESn becomes active, and the MFC2000 is inactive until the next VDD power on cycle.

Time-out Logic for the power-down lockout

There is a 1-2 second time-out on lockenn, if power down goes low enough to get latched into the battery logic,

but a lockenn doesn’t get generated by software. This will guarantee that a reset will occur if power down ever

gets set and software doesn’t set lockenn so that a reset gets generated.

There are two status bits to the backup configuration register. Bit 12 indicates that a battery reset (from the pin

batrstn) has been detected. Bit 11 indicates that a lock enable has occurred and was caused by the time-out

circuitry or a software write. To reset either of these bits a 1 must be written to the appropriate bit.

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