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HD74AC датащи(PDF) 32 Page - Hitachi Semiconductor

номер детали HD74AC
подробное описание детали  HD74AC Series Common Information
PDF  52 Pages
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производитель  HITACHI [Hitachi Semiconductor]
домашняя страница  http://www.renesas.com/eng
Logo HITACHI - Hitachi Semiconductor

HD74AC датащи(HTML) 32 Page - Hitachi Semiconductor

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Design Considerations
31
Design Considerations
Today’s system designer is faced with the problem of keeping ahead when addressing system performance
and reliability. Hitachi’s Advanced CMOS helps designers achieve these goals.
FACT (Fairchild Advanced CMOS Technology) logic was designed to alleviate many of the drawbacks
that are common to current technology logic circuits. FACT logic combines the low static power
consumption and the high noise margins of CMOS with a high fan-out, low input loading, and a 50
transmission line drive capability to offer a complete family of SSI and MSI devices.
Performance features such as advanced Schottky speeds at CMOS power levels, advanced Schottky drive,
excellent noise, ESD and latch-up immunity are characteristics that designers of state-of-the-art systems
require. FACT logic answers all of these concerns in one family of products. To fully utilize the
advantages provided by FACT, the system designer should have an understanding of the flexibility as well
as the trade-offs of CMOS design. The following section discusses common design concerns relative to the
performance and requirements of FACT.
There are five items of interest which need to be evaluated when implementing FACT devices in new
designs:
• Interfacing—interboard and technology interfaces, battery backup, and power down or live insert/
extract systems require some special thought.
• Transmission line driving—FACT has line driving capabilities superior to all CMOS families and most
TTL families.
• Noise effects—As edge rates increase, the probability of crosstalk and ground bounce problems
increases. The enhanced noise immunity and high threshold levels improve FACT’s resistance to
crosstalk problems.
• Board layout—Prudent board layout will ensure that most noise effects are minimized.
• Power supplies and decoupling—Maximize ground and V
CC traces to keep VCC/ground impedance as
low as possible; full ground/V
CC planes are best. Decouple any device driving a transmission line;
otherwise add one capacitor for every package.



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