Z8018010FSC datasheet(21/70 Pages) ZILOG

21 / 70 page

Z80180/Z8S180/Z8L180

Zilog

Enhanced Z180 Microprocessor

DS971800401

P R E L I M I N A R Y

1-21

external master during STANDBY mode, when the BREXT

bit in the CPU Control Register (CCR5) is 1.

As described previously for SLEEP and IDLE modes,

when a Z80180/Z8S180/Z8L180 leaves STANDBY mode

due to NMI Low, or when it leaves STANDBY mode due to

an enabled INTO-2 low when the IEF, flag is 1 due to an

IE instruction, it starts by performing the interrupt with the

return address being that of the instruction following the

SLP instruction. If the Z80180/Z8S180/Z8L180 leaves

STANDBY mode due to an external interrupt request that's

enabled in the INT/TRAP Control Register, but the IEF, bit

is 0 due to a DI instruction, the processor restarts by exe-

cuting the instruction(s) following the SLP instruction. If

INT0, or INT1 or 2 goes inactive before the end of the clock

stabilization delay, the Z80180/Z8S180/Z8L180 stays in

STANDBY mode.

Figure 17 shows the timing for leaving STANDBY mode

due

interrupt

request.

Note

that

the

Z80180/Z8S180/Z8L180 takes either 64 or 217 (131,072)

clocks to restart, depending on the CCR3 bit.

While the Z80180/Z8S180/Z8L180 is in STANDBY mode,

it will grant the bus to an external master if the BREXT bit

(CCR5) is 1. Figure 18 shows the timing of this sequence.

Note that the part takes 64 or 217 (131,072) clock cycles

to grant the bus depending on the CCR3 bit.

The latter (non-Quick-Recovery) case may be prohibitive

for many “demand driven” external masters. If so, QUICK

RECOVERY or IDLE mode can be used.

Figure 17. Z80180/Z8S180/Z8L180 STANDBY Mode Exit due to External Interrupt

NMI

A19-A0

HALT

Opcode Fetch or Interrupt

Acknowledge Cycle

FFFFFH

STANDBY Mode

217 or 64 Cycle Delay from INTi Asserted

INTi

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