Z8018010FSC datasheet(18/70 Pages) ZILOG

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Z80180/Z8S180/Z8L180

Enhanced Z180 Microprocessor

Zilog

1-18

P R E L I M I N A R Y

DS971800401

If an interrupt source is individually disabled, it cannot

bring the Z80180/Z8S180/Z8L180 out of SLEEP mode. If

an interrupt source is individually enabled, and the IEF bit

is 1 so that interrupts are globally enabled (by an EI in-

struction), the highest priority active interrupt will occur,

with the return address being the instruction after the SLP

instruction. If an interrupt source is individually enabled,

but the IEF bit is 0 so that interrupts are globally disabled

(by a DI instruction), the Z80180/Z8S180/Z8L180 leaves

SLEEP mode by simply executing the following instruc-

tion(s).

This provides a technique for synchronization with high-

speed external events without incurring the latency im-

posed by an interrupt response sequence. Figure 14

shows the timing for exiting SLEEP mode due to an inter-

rupt request. Note that the Z80180/Z8S180/Z8L180 takes

about 1.5 clocks to restart.

IOSTOP Mode. IOSTOP mode is entered by setting the

IOSTOP bit of the I/O Control Register (ICR) to 1. In this

case, on-chip I/O (ASCI, CSI/O, PRT) stops operating.

However, the CPU continues to operate. Recovery from

IOSTOP mode is by resetting the IOSTOP bit in ICR to 0.

SYSTEM STOP Mode. SYSTEM STOP mode is the com-

bination of SLEEP and IOSTOP modes. SYSTEM STOP

mode is entered by setting the IOSTOP bit in ICR to 1 fol-

lowed by execution of the SLP instruction. In this mode,

on-chip I/O and CPU stop operating, reducing power con-

sumption, but the PHI output continues to operate. Recov-

ery from SYSTEM STOP mode is the same as recovery

from SLEEP mode except that internal I/O sources (dis-

abled by IOSTOP) cannot generate a recovery interrupt.

IDLE

Mode.

Software

can

put

the

Z80180/Z8S180/Z8L180 into this mode by setting the

IOSTOP bit (ICR5) to 1, CCR6 to 0, CCR3 to 1 and exe-

cuting the SLP instruction. The oscillator keeps operating

but its output is blocked to all circuitry including the PHI

pin. DRAM refresh and all internal devices stop, but exter-

nal interrupts can occur. Bus granting to external masters

can occur if the BREST bit in the CPU control Register

(CCR5) was set to 1 before IDLE mode was entered.

The Z80180/Z8S180/Z8L180 leaves IDLE mode in re-

sponse to a Low on RESET, an external interrupt request

on NMI, or an external interrupt request on /INT0, /INT1 or

/INT2 that is enabled in the INT/TRAP Control Register. As

previously

described

for

SLEEP

mode,

when

the

Z80180/Z8S180/Z8L180 leaves IDLE mode due to an

NMI, or due to an enabled external interrupt request when

the IEF flag is 1 due to an EI instruction, it starts by per-

forming the interrupt with the return address being that of

the instruction after the SLP instruction.

If an external interrupt enables the INT/TRAP control reg-

ister while the IEF1 bit is 0, Z80180/Z8S180/Z8L180

leaves IDLE mode; specifically, the processor restarts by

executing the instructions following the SLP instruction.

Figure 14. SLEEP Timing

SLP 2nd Opcode

SLEEP Mode

/INTi, /NMI

A0-A19

/HALT

Opcode Fetch or Interrupt

Acknowledge Cycle

SLP 2nd Opcode Address

FFFFFH

Fetch Cycle

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