Philips Semiconductors

PMWD18UN

Dual N-channel

µTrenchMOS™ ultra low level FET

Product data

Rev. 02 — 23 February 2004

3 of 12

9397 750 12706

© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Fig 1.

Normalized total power dissipation as a

function of solder point temperature.

Fig 2.

Normalized continuous drain current as a

function of solder point temperature.

Fig 3.

Safe operating area; continuous and peak drain currents as a function of drain-source voltage.

03aa17

0

40

80

120

0

50

100

150

200

(%)

Tsp (°C)

Pder

03aa25

0

40

80

120

0

50

100

150

200

Tsp (°C)

Ider

(%)

P

der

P

tot

P

tot 25 C

°

()

-----------------------

100%

×

=

I

der

I

D

I

D25 C

°

()

-------------------

100%

×

=

003aaa258

10-2

10-1

1

10

102

10-1

1

10

102

VDS (V)

ID

(A)

DC

100 ms

10 ms

Limit RDSon = VDS / ID

1 ms

1 s

100

µs

tp = 10 µs