AD9430 datasheet(12/45 Pages) AD

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AD9430

Rev. E | Page 11 of 44

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

PIN 1

AD9430

CMOS PINOUT

TOP VIEW

(Not to Scale)

26 27

28 29 30 31 32 33 34 35 36

37 38 39 40 41

43 44 45 46 47

48 49 50

100

DRVDD

DRGND

DA4

DA3

DA2

DA1

DA0

DNC

DRGND

DNC

DCO+

DCO–

DRVDD

DRGND

OR_B

DB11

DB10

DB9

DB8

DB7

DRVDD

DRGND

DB6

DB5

DNC

AGND

DNC

AVDD

AGND

SENSE

VREF

AGND

AVDD

AGND

AVDD

AGND

VIN+

VIN–

AGND

AVDD

AGND

NOTES

1. THE AD9430 HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF

THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF

THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL

TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE

SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE

DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.

Figure 4. CMOS Dual-Mode Pin Configuration

Table 7. CMOS Mode Pin Function Descriptions

Pin Number

Mnemonic

Description

Full-Scale Adjust Pin. AVDD sets fS = 0.768 V p-p differential,

GND sets fS = 1.536 V p-p differential.

2, 7, 42, 43, 65, 66, 68

DNC

Do Not Connect.

Interleaved, Parallel Select Pin. High = interleaved.

4, 9, 12, 13, 16, 17, 20, 23, 25, 26, 30, 31, 35, 38, 41, 86,

87, 91, 92, 93, 96, 97, 100

AGND1

Analog Ground.

Output Mode Select. Low = dual-port CMOS, high = LVDS.

Data Format Select. Low = binary, high = twos complement for

both CMOS and LVDS modes.

8, 14, 15, 18, 19, 24, 27, 28, 29, 34, 39, 40, 88, 89, 90, 94,

95, 98, 99

AVDD

3.3 V Analog Supply.

SENSE

Reference Mode Select Pin. Float for internal reference operation.

VREF

1.235 V Reference I/O—Function Dependent on SENSE.

VIN+

Analog Input—True.

VIN–

Analog Input—Complement.

DS+

Data Sync (Input)—True. Tie low if not used.

DS–2

Data Sync (Input)—Complement. Tie high if not used.

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