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AD9410

Rev. A | Page 16 of 20

THEORY OF OPERATION

The AD9410 architecture is optimized for high speed and ease

of use. The analog inputs drive an integrated high bandwidth

track-and-hold circuit that samples the signal prior to

quantization by the flash 10-bit core. For ease of use, the part

includes an on-board reference and input logic that accepts

TTL, CMOS, or PECL levels.

USING THE AD9410

Clock Input

Any high speed ADC is extremely sensitive to the quality of the

sampling clock provided by the user. A track-and-hold circuit is

essentially a mixer, and any noise, distortion, or timing jitter on

the clock combines with the desired signal at the ADC output.

For that reason, considerable care has been taken in the design

of the clock input of the AD9410, and the user is advised to give

commensurate thought to the clock source. To limit SNR

degradation to less than 1 dB, a clock source with less than

1.25 ps rms jitter is required for sampling at Nyquist (for

example, the Valpey Fisher VF561). Note that required jitter

accuracy is a function of input frequency and amplitude. Refer

to the Analog Devices, Inc. AN-501 application note, Aperture

Uncertainty and ADC System Performance

, for more

information.

The clock input is fully TTL/CMOS compatible. The clock

input can be driven differentially or with a single-ended signal.

Best performance is obtained when driving the clock differentially.

Both clock inputs are self-biased to 1/3 × VCC by a high impedance

resistor divider (see the Equivalent Circuits section). Single-

ended clocking, which can be appropriate for lower frequency

or nondemanding applications, is accomplished by driving the

clock input directly and placing a 0.1 μF capacitor at CLOCK.

CLK+

CLK–

AD9410

TTL/

CMOS

GATE

0.1µF

Figure 26. Driving Single-Ended Clock Input at TTL/CMOS Levels

An example where the clock is obtained from a PECL driver is

shown in Figure 27. Note that the PECL driver is ac-coupled to

the clock inputs to minimize input current loading. The

AD9410 can be dc-coupled to PECL logic levels, resulting in the

clock input currents increasing to approximately 8 mA typical,

which is due to the difference in dc bias between the clock

inputs and a PECL driver (see the Equivalent Circuits section).

CLK+

CLK–

AD9410

PECL

GATE

0.1µF

GND

510Ω

Figure 27. Driving the Clock Inputs Differentially

ANALOG INPUT

The analog input to the AD9410 is a differential buffer. For best

dynamic performance, impedances at AIN and AIN should

match. The analog input has been optimized to provide

superior wideband performance and requires that the analog

inputs be driven differentially. SNR and SINAD performance

degrades significantly if the analog input is driven with a single-

ended signal. A wideband transformer, such as Mini-Circuits

ADT1-1WT, can be used to provide the differential analog

inputs for applications that require a single-ended-to-

differential conversion. Both analog inputs are self-biased by an

on-chip resistor divider to nominal 3 V (see the Equivalent

Circuits section).

Special care was taken in the design of the Analog Input section

of the AD9410 to prevent damage and corruption of data when

the input is overdriven. The nominal input range is 1.5 V diff p-p.

The nominal differential input range is 768 mV p-p × 2.

2.616

3.384

3.000

AIN

Figure 28. Typical Analog Input Levels

DIGITAL OUTPUTS

The digital outputs are TTL/CMOS compatible for lower power

consumption. The outputs are biased from a separate supply

(VDD), allowing easy interface to external logic. The outputs are

CMOS devices that swing from ground to VDD (with no dc

load). It is recommended to minimize the capacitive load the

ADC drives by keeping the output traces short (<1 inch, for a

total CLOAD < 5 pF). It is also recommended to place low value

(20 Ω) series damping resistors on the data lines to reduce

switching transient effects on performance.

CLOCK OUTPUTS (DCO, DCO)

The input clock is divided by two and available off-chip at DCO

and DCO. These clocks can facilitate latching off-chip,

providing a low skew clocking solution (see Figure 2). These

clocks can also be used in multiple AD9410 systems to

synchronize the ADCs. Depending on application, DCO or

DCO can be buffered and used to drive the DS inputs on a

second AD9410, ensuring synchronization. The on-chip clock

buffers should not drive more than 5 pF to 7 pF of capacitance

to limit switching transient effects on performance.

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