AD9410

Rev. A | Page 8 of 20

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

IDENTIFIER

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

AD9410

TOP VIEW

80-LEAD THIN QUAD FLAT PACKAGE

(Not to Scale)

AGND

AGND

DNC

AGND

AGND

AGND

AGND

AGND

AGND

CLK+

AGND

DGND

DGND

DCO

DCO

DGND

CLK–

DNC = DO NOT CONNECT.

Figure 3. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Function

1, 2, 8, 9, 12, 13, 16,

17, 20, 21, 24, 27, 28,

29, 30, 71, 72, 73, 74,

77, 78

AGND

Analog Ground.

3, 7, 14, 15

5 V Supply. (Regulate to within ±5%.)

4

Internal Reference Output.

5

Internal Reference Input.

6

DNC

Do Not Connect.

10

Analog Input—True.

11

Analog Input—Complement.

18

CLK+

Clock Input—True.

19

CLK−

Clock Input—Complement.

22

DS

Data Sync (Input)—True. Tie low if not used.

23

DS

Data Sync (Input)—Complement. Float and decouple with 0.1 μF capacitor if not used.

25, 26, 31, 32, 69, 70,

75, 76

3.3 V Analog Supply. (Regulate to within ±5%.)

33, 40, 49, 52, 59, 68

DGND

Digital Ground.

34, 41, 48, 53, 60, 67

3.3 V Digital Output Supply. (2.5 V to 3.6 V)

35 to 39

42 to 46

47

Data Overrange for Channel B.

50

DCO

Clock Output—Complement.