AD9460 datasheet(21/33 Pages) AD

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AD9460

Rev. 0 | Page 20 of 32

THEORY OF OPERATION

The AD9460 architecture is optimized for high speed and ease

of use. The analog inputs drive an integrated, high bandwidth

track-and-hold circuit that samples the signal prior to quantization

by the 16-bit pipeline ADC core. The device includes an on-board

reference and input logic that accepts TTL, CMOS, or LVPECL

levels. The digital output logic levels are user selectable as standard

3 V CMOS or LVDS (ANSI-644 compatible) via the OUTPUT

MODE pin.

ANALOG INPUT AND REFERENCE OVERVIEW

A stable and accurate 0.5 V band gap voltage reference is built

into the AD9460. The input range can be adjusted by varying

the reference voltage applied to the AD9460, using either the

internal reference or an externally applied reference voltage.

The input span of the ADC tracks reference voltage changes

linearly.

Internal Reference Connection

A comparator within the AD9460 detects the potential at the

SENSE pin and configures the reference into three possible states,

summarized in Table 9. If SENSE is grounded, the reference

amplifier switch is connected to the internal resistor divider (see

Figure 44), setting VREF to ~1.7 V. If a resistor divider is

connected as shown in Figure 45, the switch again sets to the

SENSE pin. This puts the reference amplifier in a noninverting

mode with the VREF output defined as

VREF = 0.5 V ×

⎟

⎠

⎞

⎜

⎝

⎛ +

In all reference configurations, REFT and REFB drive the

analog-to-digital conversion core and establish its input span.

The input range of the ADC always equals twice the voltage at

the reference pin for either an internal or an external reference.

Internal Reference Trim

The internal reference voltage is trimmed during the production

test; therefore, there is little advantage to the user supplying an

external voltage reference to the AD9460. The gain trim is

performed with the AD9460 input range set to 3.4 V p-p

nominal (SENSE connected to AGND). Because of this trim,

and the maximum ac performance provided by the 3.4 V p-p

analog input range, there is little benefit to using analog input

ranges <2 V p-p. However, reducing the range can improve SFDR

performance in some applications. Likewise, increasing the

range up to 3.4 V p-p can improve SNR. Users are cautioned

that the differential nonlinearity of the ADC varies with the

reference voltage. Configurations that use <2.0 V p-p can

exhibit missing codes and, therefore, degraded noise and

distortion performance.

10µF

0.1µF

VREF

SENSE

0.5V

AD9460

VIN–

VIN+

REFT

0.1µF

10µF

0.1µF

REFB

SELECT

LOGIC

ADC

CORE

Figure 44. Internal Reference Configuration

10µF

0.1µF

VREF

SENSE

0.5V

AD9460

VIN–

VIN+

REFT

0.1µF

10µF

0.1µF

REFB

SELECT

LOGIC

ADC

CORE

Figure 45. Programmable Reference Configuration

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