AD9460 datasheet(12/33 Pages) AD

12 / 33 page

AD9460

Rev. 0 | Page 11 of 32

Pin No.

Mnemonic

Description

REFB

Differential Reference Output. Decoupled to ground with a 0.1 μF capacitor and to REFT (Pin

10) with 0.1 μF and 10 μF capacitors.

12 to 17, 25 to 31, 35, 37

AVDD2

5.0 V Analog Supply (±5%).

VIN+

Analog Input—True.

VIN−

Analog Input—Complement.

CLK+

Clock Input—True.

CLK−

Clock Input—Complement.

47, 63, 75, 87

DRGND

Digital Output Ground.

48, 64, 76, 88

DRVDD

3.3 V Digital Output Supply (3.0 V to 3.6 V).

DCO−

Data Clock Output—Complement.

DCO+

Data Clock Output—True.

D0+ (LSB)

D0 True Output Bit (CMOS Levels).

D1+

D1 True Output Bit.

D2+

D2 True Output Bit.

D3+

D3 True Output Bit.

D4+

D4 True Output Bit.

D5+

D5 True Output Bit.

D6+

D6 True Output Bit.

D7+

D7 True Output Bit.

D8+

D8 True Output Bit.

D9+

D9 True Output Bit.

D10+

D10 True Output Bit.

D11+

D11 True Output Bit.

D12+

D12 True Output Bit.

D13+

D13 True Output Bit.

D14+

D14 True Output Bit.

D15+ (MSB)

D15 True Output Bit.

OR+

Out-of-Range True Output Bit.

100

SFDR

SFDR Control Pin. CMOS-compatible control pin for optimizing the configuration of the

AD9460 analog front end. Connecting SFDR to AGND optimizes SFDR performance for

applications with analog input frequencies <200 MHz for 80 MSPS and 105 MSPS speed

grades. For applications with analog inputs >200 MHz, connect this pin to AVDD1 for

optimum SFDR performance; power dissipation from AVDD2 increases by ~70 mW for the

AD9460BSVZ-80 and ~20 mW for the AD9460BSVZ-105.

AD9460 датащи(PDF) 12 Page - Analog Devices

AD9460 датащи(HTML) 12 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

датащи скачать

ссылки URL