AD9601 datasheet(24/33 Pages) AD

24 / 33 page

AD9601

Rev. 0 | Page 23 of 32

MEMORY MAP

READING THE MEMORY MAP TABLE

Each row in the memory map table has eight address locations.

The memory map is roughly divided into three sections: chip

configuration register map (Address 0x00 to Address 0x02),

transfer register map (Address 0xFF), and program register map

(Address 0x08 to Address 0x2A).

The Addr (Hex) column of the memory map indicates the

column shows the default hexadecimal value that is already

written into the register. The Bit 7 (MSB) column is the start of

the default hexadecimal value given. For example, Hexadecimal

Address 0x09, clock, has a hexadecimal default value of 0x01.

This means Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0,

Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. The

default value enables the duty cycle stabilizer. Overwriting this

default so that Bit 0 = 0 disables the duty cycle stabilizer. For more

information on this and other functions, consult the Interfacing

to High Speed ADCs via SPI user manual at www.analog.com.

RESERVED LOCATIONS

Undefined memory locations should not be written to other

than their default values suggested in this data sheet. Addresses

that have values marked as 0 should be considered reserved and

have a 0 written into their registers during power-up.

DEFAULT VALUES

Coming out of reset, critical registers are preloaded with default

values. These values are indicated in Table 12. Other registers

do not have default values and retain the previous value when

exiting reset.

LOGIC LEVELS

An explanation of various registers follows: “Bit is set” is

synonymous with “bit is set to Logic 1” or “writing Logic 1 for

the bit.” Similarly, “clear a bit” is synonymous with “bit is set to

Logic 0” or “writing Logic 0 for the bit.”

Table 12. Memory Map Register

Addr

(Hex)

Parameter Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

Default

Value

(Hex)

Default Notes/

Comments

Chip Configuration Registers

chip_port_config

LSB

first

Soft reset

LSB first

0x18

The nibbles

should be

mirrored by the

user so that LSB

or MSB first mode

registers correctly,

regardless of shift

mode.

chip_id

8-bit chip ID, Bits[7:0]

AD9601 = 0x36

Read-

only

Default is unique

chip ID, different

for each device.

This is a read-

only register.

chip_grade

Speed grade:

01 = 200 MSPS

10 = 250 MSPS

Read-

only

Child ID used to

differentiate

graded devices.

Transfer Register

device_update

transfer

0x00

Synchronously

transfers data

from the master

shift register to

the slave.

ADC Functions

modes

PDWN:

0 = full

(default)

1 =

standby

Internal power-down mode:

000 = normal (power-up, default)

001 = full power-down

010 = standby

011 = normal (power-up)

Note: external PDWN pin overrides

this setting

0x00

Determines

various generic

modes of chip

operation.

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