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T0504SP датащи(PDF) 4 Page - Chip Integration Technology Corporation

номер детали T0504SP
подробное описание детали  Ultra-Low Capacitance ESD Protection Device
PDF  8 Pages
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производитель  CITC [Chip Integration Technology Corporation]
домашняя страница  http://www.citcorp.com.tw/english/index.php
Logo CITC - Chip Integration Technology Corporation

T0504SP датащи(HTML) 4 Page - Chip Integration Technology Corporation

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4
Application Information
Pin Connection in PCB
lines simultaneously. The pin connection is shown
in the figure below.
Four parallel data lines, from inner IC to I/O port
connector,
coule connect to T0504SP four I/O pins
directly. Pin 3 of T0504SP is the GND pin, which
should connect to the
GND of PCB. The wire should
be as short as possible in order to minimize the
parasitic inductance.
PCB Layout Guidelines
For optimum ESD protection and the whole circuit
performance, the following PCB layout guidelines are
recommended:
should be as short as possible. It could
reduce the
ESD transient return path to GND.
The vias connecting T0504SP GND pins to the
PCB GND should be wide
.
Place
possible. It could reduce the parasitic inductance
and restrict ESD coupling into adjacent traces.
Avoid running critical signals near board edges.
T0504SP GND pin to the PCB GND rail path
T0504SP as close to the connector port as
T0504SP provides ESD protection for four data
I/O1
I/O2
I/O4
I/O3
F
p
igure 1 T0504SP in connection in PCB
Ultra-Low Capacitance ESD Protection Device
Chip Integration Technology Corporation
GND
To I/O Port
Connector
Date lines
To I/O Port
Connector
Date lines
To Inner IC
Date lines
To Inner IC
Date lines
T0504SP
□
□
□
□
Document ID : DS-22V15
Revised Date : 2017/07/20
Revision : C



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