AD6652BBC datasheet(66/76 Pages) AD

номер детали	AD6652BBC

подробное описание детали	12-Bit, 65 MSPS IF to Baseband Diversity Receiver

PDF	76 Pages

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производитель	AD [Analog Devices]

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AD6652

Rev. 0 | Page 66 of 76

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Table 29. Memory Map for Output Port Control Regist

Address

Bit Width

LHB A Control Register

LHB A enable1

2–1:

LHB A signal interleaving

All 4 channels

Channels 0, 1, 2

Channels 0, 1

Channel 0

Bypass LHB A1

LHB B Control Register

LHB B enable1

LHB B signal interleaving

Channels 2, 3

Channel 2

Bypass LHB B1

AGC A Control Register

7–5:

Output word length

111

4 bits

110

5 bits

101

6 bits

100

7 bits

011

8 bits

010

10 bits

001

12 bits

000

16 bits

Clipping error

Maintain level of clipping error

vel

Maintain output signal le

Sync now

Init on sync

First sync only

Bypass

AGC A Hold-Off Counter

15–0:

Hold-off value

AGC A Desired Level

7–0:

Desired output power level or clipping energy (R parameter)

AGC A Signal Gain

11–0:

Gs parameter

AGC A Loop Gain

7–0:

K parameter

AGC A Pole Location

7–-0:

P parameter

AGC A Average Samples

5–2:

Scale for CIC decimator

1–0:

Number of averaging samples

AGC A Update Decimation

11–0:

CIC decimation ratio

AGC B Control Register

7–5:

Output word length

111

4 bits

110

5 bits

101

6 bits

100

7 bits

011

8 bits

010

10 bits

001

12 bits

000

16 bits

Clipping error

Maintain level of clipping error

Maintain output signal level

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