AD6652BBC datasheet(51/76 Pages) AD

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AD6652

Rev. 0 | Page 51 of 76

PCLKn

PxREQ

PxIQ

PxCH[1:0]

tDPP

I[15:0]

Q[15:0]

tDPIQ

PxCH[1:0] =

Channel #

tDPCH

PxACK

Px[15:0]

DPREQ

Figure 55. Channel Mode Interleaved Format

The 8-bit concurrent format provides 8 bits of I data and 8 bits

of Q data simultaneously during one PCLK cycle, also triggered

on the rising edge of PCLK. The I byte occupies the most

significant byte of the port, while the Q byte occupies the least

nificant byte. The PAIQ and PBIQ output indicator pins are

t high during the PCLK cycle. Note that if data from multiple

channels is output consecutively, the PAIQ and PBIQ output

indicator pins remain high until data from all channels has been

output.

AGC MODE

sig

PxCH[1:0]

PCLKn

tDPREQ

PxREQ

PxACK

tDPP

Px[15:0]

I[15:8]

Q[7:0]

PxIQ

tDPIQ

PxCH[1:0] =

Channel #

tDPCH

Figure 56. Channel Mode 8I/8Q Parallel Format

The PACH[1:0] and PBCH[1:0] pins provide a 2-bit binary

value indicating the source channel of the data currently being

output.

Care should be taken to read data from the port as soon as

possible. If not, the sample will be overwritten when the next

new data sample arrives. This occurs on a per-channel basis;

that is, a Channel 0 sample is overwritten only by a new

Channel 0 sample, and so on.

The order of data output is dependent on when data arrived at

the port, which is a function of total decimation rate, start hold-

off values, and so on. Priority order is, from highest to lowest,

Channels 0, 1, 2, and 3.

els. AGC A accepts data from

d to

red such t

neration of output samples from

annels is out o

hase (by typically 180°). Each parallel

n provide da

either one or both AGCs. Bit 1 and

f Register Add

ses 0x1A (Port A) and 0x1C (Port B)

l the inclusion f data from AGCs A and B, respectively.

ode provides only one I&Q format, which is similar to

-bit interleave

ormat of channel mode. When both REQ

K are asserte

he next rising edge of PCLK triggers the

of a 16-bit AGC I word for one PCLK cycle. The PAIQ

and PBIQ output indicator pins are high during this cycle, and

are low otherwise. A 16-bit AGC Q word is provided during the

subsequent PCLK cycle. If the AGC gain word has been updated

since the last sample, a 12-bit RSSI word is provided during the

PCLK cycle following the Q word of 12 MSBs of the parallel

port data pins. This RSSI word is the bit-inverse of the signal

gain word used in the gain multiplier of the AGC.

The data provided by the PACH[1:0] and PBCH[1:0] pins in

AGC mode is different than that provided in channel mode. In

AGC mode, PACH[0] and PBCH[0] indicate the AGC source of

the data currently being output (0 = AGC A, 1 = AGC B).

PACH[1] and PBCH[1] indicate whether the current data is an

I/Q word or an AGC RSSI word (0 = I/Q word, 1 = AGC RSSI

word). The two different AGC outputs are shown in Figure 57

and Figure 58.

Parallel port channel mode is selected by clearing Bit 0 of

Addresses 0x1A and 0x1C for Parallel Ports A and B, respec-

tively. I and Q data output in AGC mode are output from the

AGC, not the individual chann

Channel 0 to Channel 3, while AGC B accepts data from

Channel 2 and Channel 3. Each pair of channels is require

be configu

hat the ge

the ch

f p

port ca

ta from

Bit 2 o

res

contro

AGC m

the 16

d f

and AC

d, t

output

PCLKn

PxREQ

PxACK

Px[15:0]

PxIQ

PxCH[1:0]

tDPREQ

tDPP

I[15:0]

Q[15:0]

tDPIQ

PxCH[0] = AGC #

PxCH[1] = 0

tDPCH

Figure 57. AGC with No RSSI Word

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