AD9653 datasheet(39/42 Pages) AD

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AD9653

Data Sheet

Rev. E | Page 38 of 41

precedence over the 2× driver strength on FCO and DCO when

both the output driver termination and output drive are selected.

Output Phase (Register 0x16)

Bit 7—Open

Bits[6:4]—Input Clock Phase Adjust

When the clock divider (Register 0x0B) is used, the applied

clock is at a higher frequency than the internal sampling clock.

clock the sampling occurs. This is applicable only when the

clock divider is used. It is prohibited to select a value for Bits[6:4]

that is greater than the value of Bits[2:0], Register 0x0B.

Table 21. Input Clock Phase Adjust Options

Input Clock Phase

Adjust, Bits[6:4]

Number of Input Clock Cycles of

Phase Delay

000 (Default)

001

010

011

100

101

110

111

Bits[3:0]—Output Clock Phase Adjust

Table 22. Output Clock Phase Adjust Options

Output Clock (DCO),

Phase Adjust, Bits[3:0]

DCO Phase Adjustment (Degrees

Relative to D0±x/D1±x Edge)

0000

0001

0010

120

0011 (Default)

180

0100

240

0101

300

0110

360

0111

420

1000

480

1001

540

1010

600

1011

660

Serial Output Data Control (Register 0x21)

The serial output data control register is used to program the

AD9653 in various output data modes depending upon the data

capture solution. Table 23 describes the various serialization

options available in the AD9653.

Sample Rate Override (Register 0x100)

This register is designed to allow the user to downgrade the device

(that is, establish lower power) for applications that do not require a

full sample rate. Settings in this register are not initialized until Bit 0

of the transfer register (Register 0xFF) is set to 1.

This function does not affect the sample rate; it affects the

maximum sample rate capability of the ADC, as well as the

resolution.

User Input/Output Control 2 (Register 0x101)

Bits[7:1]—Open

Bit 0—SDIO Pull-Down

Bit 0 can be set to disable the internal 30 kΩ pull-down on the

SDIO pin, which can be used to limit the loading when many

devices are connected to the SPI bus.

User Input/Output Control 3 (Register 0x102)

Bits[7:4]—Open

Bit 3—VCM Power-Down

Bit 3 can be set high to power down the internal VCM generator.

This feature is used when applying an external reference.

Bits[2:0]—Open

Table 23. SPI Register Options

Serialization Options Selected

Contents

Serial Output Number

of Bits (SONB)

Frame Mode

Serial Data Mode

DCO Multiplier

Timing Diagram

0x30

16-bit

1×

DDR two-lane, bytewise

4 × fS

Figure 2 (default setting)

0x20

16-bit

1×

DDR two-lane, bitwise

4 × fS

Figure 2

0x10

16-bit

1×

SDR two-lane, bytewise

8 × fS

Figure 2

0x00

16-bit

1×

SDR two-lane, bitwise

8 × fS

Figure 2

0x34

16-bit

2×

DDR two-lane, bytewise

4 × fS

Figure 3

0x24

16-bit

2×

DDR two-lane, bitwise

4 × fS

Figure 3

0x14

16-bit

2×

SDR two-lane, bytewise

8 × fS

Figure 3

0x04

16-bit

2×

SDR two-lane, bitwise

8 × fS

Figure 3

0x40

16-bit

1×

DDR one-lane, wordwise

8 × fS

Figure 4

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