AD9653 datasheet(4/42 Pages) AD

4 / 42 page

Data Sheet

AD9653

Rev. E | Page 3 of 41

REVISION HISTORY

3/16—Rev. D to Rev. E

Changes to General Description Section .......................................1

Changes to Figure 15 ......................................................................15

Changes to Table 13 ........................................................................29

11/15—Rev. C to Rev. D

Changes to General Description Section .......................................1

Added Note 4, Table 6.......................................................................8

Changes to Digital Outputs and Timing Section........................28

8/15—Rev. B to Rev. C

Change to Applications Section ......................................................1

Change to Jitter Considerations Section ......................................25

7/15—Rev. A to Rev. B

Added Patent Note, Note 1...............................................................1

Change to Applications Section and General Description

Section ................................................................................................1

Change to Effective Number of Bits (ENOB) Parameter,

Table 3.................................................................................................5

Changes to Table 5 ............................................................................7

Change to Table 8............................................................................11

Changes to Reading the Memory Map Register Table Section

and Channel-Specific Registers Section.......................................32

Changes to Table 19 ........................................................................33

Changes to Device Index (Register 0x04, Register 0x05)

Section ..............................................................................................36

Changes to Clock Stability Considerations Section....................38

11/14—Rev. 0 to Rev. A

Changed Output Voltage (1.0 V Mode) from 1.01 V to

1.02 V (max); Table 1........................................................................3

Changes to Table 3 ............................................................................5

Added tPD of 1.5 ns (min) and 3.1 ns (max); Table 6 ....................8

Changed tSSYNC from 0.24 ns (typ) to 1.2 ns (min) and Changed

tHSYNC from 0.40 ns (typ) to −0.2 ns (min); Table 7.......................9

Changes to Table 10 ........................................................................12

Changes to Clock Input Options Section ....................................24

Changes to Digital Outputs and Timing Section........................27

Changes to Table 13 ........................................................................28

Changes to Table 14 ........................................................................29

AD9653 датащи(PDF) 4 Page - Analog Devices